Patent US2859118A successfully refreshed from Google Patents.
Patent US6110774A successfully refreshed from Google Patents.
US6110774A
Expired / Lapsed
US
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Method of forming a bit line over capacitor array of memory cells and an array of bit line over capacitor array of memory cells
Assignee: Micron Technology Inc
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Filing: 1997-08-27
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Granted: 2000-08-29
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Expires: 2017-08-27
Abstract
Abstract A semiconductor memory device includes, a) a semiconductor substrate; b) a field effect transistor gate positioned outwardly of the semiconductor substrate; c) opposing active areas formed within the semiconductor substrate on opposing sides of the gate; d) a capacitor electrically connected with one of the active areas; the capacitor comprising an inner storage node, a capacitor dielectric layer, and an outer cell node; the inner storage node electrically connecting with the one active area, the inner storage node having an upper surface at an elevation; e) a bit line; f) a dielectric insulating layer positioned intermediate the bit line and the other active area; and g) an electrically conductive bit line plug extending through the insulating layer to contact with the other active area and electrically interconnect the bit line with the other active area, the bit line plug being homogeneous in composition between the other active area and the elevation of the inner storage node upper surface. A method of producing such a construction is also disclosed.
Inventors
- 👤 Mark Jost
- 👤 Charles Dennison
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 04:49
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10B12/30; H10B12/31; H10D; H10D1/00; H10D1/60; H10D1/68; H10D1/692; H10D1/711; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/056; H10D1/712; H10D1/714; H10D1/716; Y; Y10; Y10S; Y10S148/00; Y10S148/05
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
129 words
A method of forming a bit line plug to an active region, comprising the following steps: forming a word line over a semiconductor wafer; forming a first active region and a second active region associated with the word line; forming a layer of electrically insulating material over the word line and active regions; forming a bit line contact opening through the insulating material layer to the second active region; forming an electrically conductive layer over the insulating material layer and within the bit line contact opening, the electrically conductive layer within the bit line contact opening ultimately forming a bit line plug; and using a single photomasking step, removing portions of the electrically conductive layer and the insulating material to form a capacitor opening to the first active region.
Claim 2
Independent Claim
129 words
A method of forming a bit line plug to an active region, comprising the following steps: forming a word line over a semiconductor wafer; forming a first active region and a second active region associated with the word line; forming a layer of electrically insulating material over the word line and active regions; forming a bit line contact opening through the insulating material layer to the second active region; forming an electrically conductive layer over the insulating material layer and within the bit line contact opening, the electrically conductive layer within the bit line contact opening ultimately forming a bit line plug; and using a single photomasking step, removing portions of the electrically conductive layer and the insulating material to form a capacitor opening to the first active region.
Claim 3
Independent Claim
124 words
A method of forming an array of bit line plugs, comprising the following steps: forming an array of word lines over a semiconductor wafer; forming first and second active regions associated with each of the word lines; forming a layer of electrically insulating material over the word lines and active regions; forming bit line contact openings through the insulating material layer to the second active regions; forming an electrically conductive layer over the insulating material layer and within the bit line contact openings, the electrically conductive layer within the bit line contact openings ultimately forming bit line plugs; and using a single photomasking step, removing portions of the electrically conductive layer and the insulating material to form capacitor openings to the first active regions.
Claim 4
Independent Claim
124 words
A method of forming an array of bit line plugs, comprising the following steps: forming an array of word lines over a semiconductor wafer; forming first and second active regions associated with each of the word lines; forming a layer of electrically insulating material over the word lines and active regions; forming bit line contact openings through the insulating material layer to the second active regions; forming an electrically conductive layer over the insulating material layer and within the bit line contact openings, the electrically conductive layer within the bit line contact openings ultimately forming bit line plugs; and using a single photomasking step, removing portions of the electrically conductive layer and the insulating material to form capacitor openings to the first active regions.
Claim 5
Independent Claim
173 words
A method of forming a bit line p lug to an active region, comprising the following steps: forming a word line over a semiconductor wafer; forming a first active region and a second active region associated with the word line; forming a layer of electrically insulating material over the word line and active regions, the layer of electrically insulating material comprising an upper surface at a first level, the layer of electrically insulating material comprising borophosphosilicate glass; forming a bit line contact opening through the insulating material layer to the second active region; forming an electrically conductive layer over the insulating material layer and within the bit line contact opening, the electrically conductive layer within the bit line contact opening ultimately forming a bit line plug; forming a capacitor opening through the electrically conductive layer and through the insulating material to the first active region; and after forming the capacitor opening, chemical-mechanical polishing the electrically conductive layer to below the first level of the upper surface of the layer of the insulating material.
Claim 6
Independent Claim
173 words
A method of forming a bit line p lug to an active region, comprising the following steps: forming a word line over a semiconductor wafer; forming a first active region and a second active region associated with the word line; forming a layer of electrically insulating material over the word line and active regions, the layer of electrically insulating material comprising an upper surface at a first level, the layer of electrically insulating material comprising borophosphosilicate glass; forming a bit line contact opening through the insulating material layer to the second active region; forming an electrically conductive layer over the insulating material layer and within the bit line contact opening, the electrically conductive layer within the bit line contact opening ultimately forming a bit line plug; forming a capacitor opening through the electrically conductive layer and through the insulating material to the first active region; and after forming the capacitor opening, chemical-mechanical polishing the electrically conductive layer to below the first level of the upper surface of the layer of the insulating material.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-08-29 | 2004-02-28 | 2004-08-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-08-29 | 2008-02-28 | 2008-08-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-08-29 | 2012-02-28 | 2012-08-29 | $7700.00 | Window Closed / Lapsed |