Method of forming a bit line over capacitor array of memory cells

Claim 1

A method of forming a bit line over capacitor array of memory cells comprising: providing an array of substantially electrically isolated word lines atop a semiconductor wafer; providing active areas about the word lines to define an array of memory cell FETs, the active areas being defined by a first active region for electrical connection with a memory cell capacitor and a second active region for electrical connection with a bit line; providing a planarized first layer of an insulating material over the word lines and active areas, the planarized layer of insulating material having an upper surface which is above the word lines; providing first contact openings through the first layer of insulating material to second active regions; providing first conductive material pillars within the first contact openings, the first pillars having upper surfaces which are elevationally above the word lines; providing a covering layer of insulating material over the planarized first layer of insulating material and first pillars; providing capacitor contact openings through the covering layer to electrically connect with the first active regions; providing capacitors within the capacitor contact openings; providing an overlying layer of insulating material over the covering layer of insulating material and over the capacitors; providing bit line contact openings through the overlying layer and the covering layer to the first pillar upper surfaces; and providing a digit line layer of conductive material atop the wafer and within the bit line contact openings, the digit line layer electrically connecting with the first pillar upper surfaces.

Claim 2

A method of forming a bit line over capacitor array of memory cells comprising: providing an array of substantially electrically isolated word lines atop a semiconductor wafer; providing active areas about the word lines to define an array of memory cell FETs, the active areas being defined by a first active region for electrical connection with a memory cell capacitor and a second active region for electrical connection with a bit line; providing a planarized first layer of an insulating material over the word lines and active areas, the planarized layer of insulating material having an upper surface which is above the word lines; providing first contact openings through the first layer of insulating material to second active regions; providing first conductive material pillars within the first contact openings, the first pillars having upper surfaces which are elevationally above the word lines; providing a covering layer of insulating material over the planarized first layer of insulating material and first pillars; providing capacitor contact openings through the covering layer to electrically connect with the first active regions; providing capacitors within the capacitor contact openings; providing an overlying layer of insulating material over the covering layer of insulating material and over the capacitors; providing bit line contact openings through the overlying layer and the covering layer to the first pillar upper surfaces; and providing a digit line layer of conductive material atop the wafer and within the bit line contact openings, the digit line layer electrically connecting with the first pillar upper surfaces.

Claim 4

A method of forming a bit line over capacitor array of memory cells comprising: providing an array of substantially electrically isolated word lines atop a semiconductor wafer; providing active areas about the word lines to define an array of memory cell FETs, the active areas being defined by a first active region for electrical connection with a memory cell capacitor and a second active region for electrical connection with a bit line; providing a planarized first layer of an insulating material over the word lines and active areas, the planarized layer of insulating material having an upper surface which is above the word lines; providing first contact openings through a first layer of insulating material to second active regions; providing first conductive material pillars within the first contact openings, the first pillars having upper surfaces which are elevationally above the word lines; providing a covering layer of insulating material over the planarized first layer of insulating material and first pillars; providing capacitor contact openings through the covering layer to electrically connect with the first active regions; providing a layer of conductive material over the covering layer of insulating material and within the capacitor contact openings, the layer of conductive material having an outer surface; removing conductive material from atop the covering layer to define isolated cell storage node containers electrically connecting with the first active regions; providing a capacitor cell dielectric layer on the wafer atop the isolated storage nodes, insulating material of the covering layer being interposed between the first pillar upper surfaces and the capacitor cell dielectric layer; providing a conductive capacitor cell layer atop the capacitor cell dielectric layer to define an array of memory cell capacitors; providing an overlaying layer of insulating material over the conductive capacitor cell layer; providing bit line contact openings through the overlying layer, conductive capacitor cell layer, cell capacitor dielectric layer and covering layer to the first pillar upper surfaces, the bit line contact openings having sidewalls, the bit line contact opening sidewalls including exposed edges of the conductive capacitor cell layer; electrically insulating exposed edges of the conductive capacitor cell layer within the bit line contact openings; and after electrically insulating the exposed edges, providing a digit line layer of conductive material atop the wafer and within the bit line contact openings, the digit line layer electrically connecting with the first pillar upper surfaces.

Claim 5

A method of forming a bit line over capacitor array of memory cells comprising: providing an array of substantially electrically isolated word lines atop a semiconductor wafer; providing active areas about the word lines to define an array of memory cell FETs, the active areas being defined by a first active region for electrical connection with a memory cell capacitor and a second active region for electrical connection with a bit line; providing a planarized first layer of an insulating material over the word lines and active areas, the planarized layer of insulating material having an upper surface which is above the word lines; providing first contact openings through a first layer of insulating material to second active regions; providing first conductive material pillars within the first contact openings, the first pillars having upper surfaces which are elevationally above the word lines; providing a covering layer of insulating material over the planarized first layer of insulating material and first pillars; providing capacitor contact openings through the covering layer to electrically connect with the first active regions; providing a layer of conductive material over the covering layer of insulating material and within the capacitor contact openings, the layer of conductive material having an outer surface; removing conductive material from atop the covering layer to define isolated cell storage node containers electrically connecting with the first active regions; providing a capacitor cell dielectric layer on the wafer atop the isolated storage nodes, insulating material of the covering layer being interposed between the first pillar upper surfaces and the capacitor cell dielectric layer; providing a conductive capacitor cell layer atop the capacitor cell dielectric layer to define an array of memory cell capacitors; providing an overlaying layer of insulating material over the conductive capacitor cell layer; providing bit line contact openings through the overlying layer, conductive capacitor cell layer, cell capacitor dielectric layer and covering layer to the first pillar upper surfaces, the bit line contact openings having sidewalls, the bit line contact opening sidewalls including exposed edges of the conductive capacitor cell layer; electrically insulating exposed edges of the conductive capacitor cell layer within the bit line contact openings; and after electrically insulating the exposed edges, providing a digit line layer of conductive material atop the wafer and within the bit line contact openings, the digit line layer electrically connecting with the first pillar upper surfaces.

Claim 10

A method of forming a bit line over capacitor array of memory cells comprising: providing an array of substantially electrically isolated word lines atop a semiconductor wafer; providing active areas about the word lines to define an array of memory cell FETs, the active areas being defined by a first active region for electrical connection with a memory cell capacitor and a second active region for electrical connection with a bit line; providing a planarized first layer of an insulating material over the word lines and active areas, the planarized layer of insulating material having an upper surface which is above the word lines; providing first contact openings through the first layer of insulating material to second active regions; providing first conductive material pillars within the first contact openings, the first pillars having upper surfaces which are elevationally above the word lines; providing a covering layer of insulating material over the planarized first layer of insulating material and first pillars; providing capacitor contact openings through the covering layer to electrically connect with the first active regions; providing a layer of conductive material over the covering layer of insulating material and within the capacitor contact openings, the layer of conductive material having an outer surface; removing conductive material from atop the covering layer to define isolated cell storage node containers electrically connecting with the first active regions, the isolated call storage node containers having internal sidewalls and external sidewalls; removing insulating material of the covering layer to expose only a portion of the external sidewalls of the isolated cell storage node containers; providing a capacitor cell dielectric layer on the wafer atop the isolated storage nodes including the exposed portions of the isolated storage node external sidewalls, insulating material of the covering layer being interposed between the first pillar upper surfaces and the capacitor cell dielectric layer; providing a conductive capacitor cell layer atop the capacitor cell dielectric layer to define an array of memory cell capacitors; providing an overlying layer of insulating material over the conductive capacitor cell layer; providing bit line contact openings through the overlying layer, conductive capacitor cell layer, cell capacitor dielectric layer and covering layer to the first pillar upper surfaces, the bit line contact openings having sidewalls, the bit line contact opening sidewalls including exposed edges of the conductive capacitor cell layer; electrically insulating exposed edges of the conductive capacitor cell layer within the bit line contact openings; and after electrically insulating the exposed edges, providing a digit line layer of conductive material atop the wafer and within the bit line contact openings, the digit line layer electrically connecting with the first pillar upper surfaces.

Claim 11

A method of forming a bit line over capacitor array of memory cells comprising: providing an array of substantially electrically isolated word lines atop a semiconductor wafer; providing active areas about the word lines to define an array of memory cell FETs, the active areas being defined by a first active region for electrical connection with a memory cell capacitor and a second active region for electrical connection with a bit line; providing a planarized first layer of an insulating material over the word lines and active areas, the planarized layer of insulating material having an upper surface which is above the word lines; providing first contact openings through the first layer of insulating material to second active regions; providing first conductive material pillars within the first contact openings, the first pillars having upper surfaces which are elevationally above the word lines; providing a covering layer of insulating material over the planarized first layer of insulating material and first pillars; providing capacitor contact openings through the covering layer to electrically connect with the first active regions; providing a layer of conductive material over the covering layer of insulating material and within the capacitor contact openings, the layer of conductive material having an outer surface; removing conductive material from atop the covering layer to define isolated cell storage node containers electrically connecting with the first active regions, the isolated call storage node containers having internal sidewalls and external sidewalls; removing insulating material of the covering layer to expose only a portion of the external sidewalls of the isolated cell storage node containers; providing a capacitor cell dielectric layer on the wafer atop the isolated storage nodes including the exposed portions of the isolated storage node external sidewalls, insulating material of the covering layer being interposed between the first pillar upper surfaces and the capacitor cell dielectric layer; providing a conductive capacitor cell layer atop the capacitor cell dielectric layer to define an array of memory cell capacitors; providing an overlying layer of insulating material over the conductive capacitor cell layer; providing bit line contact openings through the overlying layer, conductive capacitor cell layer, cell capacitor dielectric layer and covering layer to the first pillar upper surfaces, the bit line contact openings having sidewalls, the bit line contact opening sidewalls including exposed edges of the conductive capacitor cell layer; electrically insulating exposed edges of the conductive capacitor cell layer within the bit line contact openings; and after electrically insulating the exposed edges, providing a digit line layer of conductive material atop the wafer and within the bit line contact openings, the digit line layer electrically connecting with the first pillar upper surfaces.

Claim 15

A method of forming a bit line over capacitor array of memory cells comprising: providing an array of substantially electrically isolated word lines atop a semiconductor wafer; providing active areas about the word lines to define an array of memory cell FETs, the active areas being defined by a first active region for electrical connection with a memory cell capacitor and a second active region for electrical connection with a bit line; providing a planarized first layer of an insulating material over the word lines and active areas, the planarized layer of insulating material having an upper surface which is above the word lines; providing first contact openings through the first layer of insulating material to second active regions; providing first conductive material pillars within the first contact openings, the first pillars having upper surfaces which are elevationally above the word lines; providing a planarized base layer of insulating material over the planarized first layer of insulating material and first pillars, the planarized base layer having a planar uppermost region and a planar uppermost surface; providing an intermediate layer of insulating material atop the uppermost region of the planarized base layer, the insulating material of the intermediate layer being different in composition from the insulating material of the uppermost region of the base layer with the insulating material of the intermediate layer being selectively etchable relative to the insulating material of such uppermost region; providing capacitor contact openings through the intermediate layer to electrically connect with the first active regions; providing a layer of conductive material over the intermediate layer of insulating material and within the capacitor contact openings, the layer of conductive material having an outer surface; removing conductive material from atop the intermediate layer to define isolated cell storage node containers electrically connecting with the first active regions, the isolated cell storage node containers having internal sidewalls and external sidewalls; etching the intermediate layer selectively relative to the isolated capacitor storage node and uppermost region of the base layer, and using the uppermost region of the base layer as an etch stop during such etching to expose only a portion of the external sidewalls of the isolated cell storage node containers; providing a capacitor cell dielectric layer on the wafer atop the isolated storage nodes including the exposed portions of the isolated storage node external sidewalls, insulating material of the base layer being interposed between the first pillar upper surfaces and the capacitor cell dielectric layer; providing a conductive capacitor cell layer atop the capacitor cell dielectric layer to define an array of memory cell capacitors; providing an overlying layer of insulating material over the conductive capacitor cell layer; providing bit line contact openings through the overlying layer, conductive capacitor cell layer, cell capacitor dielectric layer and base layer to the first pillar upper surfaces, the bit line contact openings having sidewalls, the bit line contact opening sidewalls including exposed edges of the conductive capacitor cell layer; electrically insulating exposed edges of the conductive capacitor cell layer within the bit line contact openings; and after electrically insulating the exposed edges, providing a digit line layer of conductive material atop the wafer and within the bit line contact openings, the digit line layer electrically connecting with the first pillar upper surfaces.

Claim 16

A method of forming a bit line over capacitor array of memory cells comprising: providing an array of substantially electrically isolated word lines atop a semiconductor wafer; providing active areas about the word lines to define an array of memory cell FETs, the active areas being defined by a first active region for electrical connection with a memory cell capacitor and a second active region for electrical connection with a bit line; providing a planarized first layer of an insulating material over the word lines and active areas, the planarized layer of insulating material having an upper surface which is above the word lines; providing first contact openings through the first layer of insulating material to second active regions; providing first conductive material pillars within the first contact openings, the first pillars having upper surfaces which are elevationally above the word lines; providing a planarized base layer of insulating material over the planarized first layer of insulating material and first pillars, the planarized base layer having a planar uppermost region and a planar uppermost surface; providing an intermediate layer of insulating material atop the uppermost region of the planarized base layer, the insulating material of the intermediate layer being different in composition from the insulating material of the uppermost region of the base layer with the insulating material of the intermediate layer being selectively etchable relative to the insulating material of such uppermost region; providing capacitor contact openings through the intermediate layer to electrically connect with the first active regions; providing a layer of conductive material over the intermediate layer of insulating material and within the capacitor contact openings, the layer of conductive material having an outer surface; removing conductive material from atop the intermediate layer to define isolated cell storage node containers electrically connecting with the first active regions, the isolated cell storage node containers having internal sidewalls and external sidewalls; etching the intermediate layer selectively relative to the isolated capacitor storage node and uppermost region of the base layer, and using the uppermost region of the base layer as an etch stop during such etching to expose only a portion of the external sidewalls of the isolated cell storage node containers; providing a capacitor cell dielectric layer on the wafer atop the isolated storage nodes including the exposed portions of the isolated storage node external sidewalls, insulating material of the base layer being interposed between the first pillar upper surfaces and the capacitor cell dielectric layer; providing a conductive capacitor cell layer atop the capacitor cell dielectric layer to define an array of memory cell capacitors; providing an overlying layer of insulating material over the conductive capacitor cell layer; providing bit line contact openings through the overlying layer, conductive capacitor cell layer, cell capacitor dielectric layer and base layer to the first pillar upper surfaces, the bit line contact openings having sidewalls, the bit line contact opening sidewalls including exposed edges of the conductive capacitor cell layer; electrically insulating exposed edges of the conductive capacitor cell layer within the bit line contact openings; and after electrically insulating the exposed edges, providing a digit line layer of conductive material atop the wafer and within the bit line contact openings, the digit line layer electrically connecting with the first pillar upper surfaces.

Claim 22

A method of forming a bit line over capacitor array of memory cells comprising: providing an array of substantially electrically isolated word lines atop a semiconductor wafer; providing active areas about the word lines to define an array of memory cell FETs, the active areas being defined by a first active region for electrical connection with a memory cell capacitor and a second active region for electrical connection with a bit line; providing a planarized first layer of an insulating material over the word lines and active areas, the planarized layer of insulating material having an upper surface which is above the word lines; providing first contact openings through the first layer of insulating material to second active regions; providing first conductive material pillars within the first contact openings, the first pillars having upper surfaces which are elevationally above the word lines; providing a planarized base layer of insulating material over the planarized first layer of insulating material and first pillars, the planarized base layer having a planar uppermost region, a planar uppermost surface, and a first thickness; providing an intermediate layer of insulating material atop the uppermost region of the planarized base layer, the insulating material of the intermediate layer being different in composition from the insulating material of the uppermost region of the base layer with the insulating material of the intermediate layer being selectively etchable relative to the insulating material of such uppermost region; providing capacitor contact openings through the intermediate layer to electrically connect with the first active regions; providing a layer of conductive material over the intermediate layer of insulating material and within the capacitor contact openings, the layer of conductive material having an outer surface; removing conductive material from atop the intermediate layer to define isolated cell storage node containers electrically connecting with the first active regions, the isolated cell storage node containers having internal sidewalls and external sidewalls; etching the intermediate layer selectively relative to the isolated capacitor storage node and uppermost region of the base layer, and using the uppermost region of the base layer as an etch stop during such etching to expose only a portion of the external sidewalls of the isolated cell storage node containers; providing a capacitor cell dielectric layer on the wafer atop the isolated storage nodes including the exposed portions of the isolated storage node external sidewalls, insulating material of the base layer being interposed between the first pillar upper surfaces and the capacitor cell dielectric layer; providing a conductive capacitor cell layer atop the capacitor cell dielectric layer to define an array of memory cell capacitors, individual memory cell capacitors of the array being defined by an outwardly projecting container structure having a projecting outermost surface; providing an overlying layer of insulating material over the conductive capacitor cell layer to a second thickness above the outermost surface, the second thickness being greater than the first thickness; providing preliminary bit line contact openings through the overlying layer, conductive capacitor cell layer, and cell capacitor dielectric layer over the first pillars, the preliminary bit line contact openings having sidewalls, the preliminary bit line contact opening sidewalls including exposed edges of the conductive capacitor cell layer; electrically insulating exposed edges of the conductive capacitor cell layer; blanket etching without photomasking the base layer and overlying layer to extend the preliminary bit line contact to the first pillar upper surfaces, and leaving insulating material of the overlying layer atop the projecting outermost surfaces; and after electrically insulating the exposed edges, providing a digit line layer of conductive material atop the wafer and within the bit line contact openings, the digit line layer electrically connecting with the first pillar upper surfaces.

Claim 23

A method of forming a bit line over capacitor array of memory cells comprising: providing an array of substantially electrically isolated word lines atop a semiconductor wafer; providing active areas about the word lines to define an array of memory cell FETs, the active areas being defined by a first active region for electrical connection with a memory cell capacitor and a second active region for electrical connection with a bit line; providing a planarized first layer of an insulating material over the word lines and active areas, the planarized layer of insulating material having an upper surface which is above the word lines; providing first contact openings through the first layer of insulating material to second active regions; providing first conductive material pillars within the first contact openings, the first pillars having upper surfaces which are elevationally above the word lines; providing a planarized base layer of insulating material over the planarized first layer of insulating material and first pillars, the planarized base layer having a planar uppermost region, a planar uppermost surface, and a first thickness; providing an intermediate layer of insulating material atop the uppermost region of the planarized base layer, the insulating material of the intermediate layer being different in composition from the insulating material of the uppermost region of the base layer with the insulating material of the intermediate layer being selectively etchable relative to the insulating material of such uppermost region; providing capacitor contact openings through the intermediate layer to electrically connect with the first active regions; providing a layer of conductive material over the intermediate layer of insulating material and within the capacitor contact openings, the layer of conductive material having an outer surface; removing conductive material from atop the intermediate layer to define isolated cell storage node containers electrically connecting with the first active regions, the isolated cell storage node containers having internal sidewalls and external sidewalls; etching the intermediate layer selectively relative to the isolated capacitor storage node and uppermost region of the base layer, and using the uppermost region of the base layer as an etch stop during such etching to expose only a portion of the external sidewalls of the isolated cell storage node containers; providing a capacitor cell dielectric layer on the wafer atop the isolated storage nodes including the exposed portions of the isolated storage node external sidewalls, insulating material of the base layer being interposed between the first pillar upper surfaces and the capacitor cell dielectric layer; providing a conductive capacitor cell layer atop the capacitor cell dielectric layer to define an array of memory cell capacitors, individual memory cell capacitors of the array being defined by an outwardly projecting container structure having a projecting outermost surface; providing an overlying layer of insulating material over the conductive capacitor cell layer to a second thickness above the outermost surface, the second thickness being greater than the first thickness; providing preliminary bit line contact openings through the overlying layer, conductive capacitor cell layer, and cell capacitor dielectric layer over the first pillars, the preliminary bit line contact openings having sidewalls, the preliminary bit line contact opening sidewalls including exposed edges of the conductive capacitor cell layer; electrically insulating exposed edges of the conductive capacitor cell layer; blanket etching without photomasking the base layer and overlying layer to extend the preliminary bit line contact to the first pillar upper surfaces, and leaving insulating material of the overlying layer atop the projecting outermost surfaces; and after electrically insulating the exposed edges, providing a digit line layer of conductive material atop the wafer and within the bit line contact openings, the digit line layer electrically connecting with the first pillar upper surfaces.

Claim 29

A method of forming a bit line over capacitor array of memory cells comprising: providing an array of substantially electrically isolated word lines atop a semiconductor wafer; providing active areas about the word lines to define an array of memory cell FETs, the active areas being defined by a first active region for electrical connection with a memory cell capacitor and a second active region for electrical connection with a bit line; providing a planarized first layer of an insulating material over the word lines and active areas, the planarized layer of insulating material having an upper surface which is above the word lines; providing first contact openings through the first layer of insulating material to second active regions; providing second contact openings through the first layer of insulating material to first active regions; providing first conductive material pillars within the first contact openings, the first pillars having upper surfaces which are elevationally above the word lines; providing second conductive material pillars within the second contact openings, the second pillars having upper surfaces which are elevationally above the word lines; providing a covering layer of insulating material over the planarized first layer of insulating material and first and second pillars; providing capacitor contact openings through the covering layer to the second pillar upper surfaces; providing a layer of conductive material over the covering layer of insulating material and within the capacitor contact openings, the layer of conductive material having an outer surface; removing conductive material from atop the covering layer to define isolated cell storage node containers electrically connecting with the first active regions; providing a capacitor cell dielectric layer on the wafer atop the isolated storage nodes, insulating material of the covering layer being interposed between the first pillar upper surfaces and the capacitor cell dielectric layer; providing a conductive capacitor cell layer atop the capacitor cell dielectric layer to define an array of memory cell capacitors; providing an overlying layer of insulating material over the conductive capacitor cell layer; providing bit line contact openings through the overlying layer, conductive capacitor cell layer, cell capacitor dielectric layer and covering layer to the first pillar upper surfaces, the bit line contact openings having sidewalls, the bit line contact opening sidewalls including exposed edges of the conductive capacitor cell layer; electrically insulating exposed edges of the conductive capacitor cell layer within the bit line contact openings; and after electrically insulating the exposed edges, providing a digit line layer of conductive material atop the wafer and within the bit line contact openings, the digit line layer electrically connecting with the first pillar upper surfaces.

Claim 30

A method of forming a bit line over capacitor array of memory cells comprising: providing an array of substantially electrically isolated word lines atop a semiconductor wafer; providing active areas about the word lines to define an array of memory cell FETs, the active areas being defined by a first active region for electrical connection with a memory cell capacitor and a second active region for electrical connection with a bit line; providing a planarized first layer of an insulating material over the word lines and active areas, the planarized layer of insulating material having an upper surface which is above the word lines; providing first contact openings through the first layer of insulating material to second active regions; providing second contact openings through the first layer of insulating material to first active regions; providing first conductive material pillars within the first contact openings, the first pillars having upper surfaces which are elevationally above the word lines; providing second conductive material pillars within the second contact openings, the second pillars having upper surfaces which are elevationally above the word lines; providing a covering layer of insulating material over the planarized first layer of insulating material and first and second pillars; providing capacitor contact openings through the covering layer to the second pillar upper surfaces; providing a layer of conductive material over the covering layer of insulating material and within the capacitor contact openings, the layer of conductive material having an outer surface; removing conductive material from atop the covering layer to define isolated cell storage node containers electrically connecting with the first active regions; providing a capacitor cell dielectric layer on the wafer atop the isolated storage nodes, insulating material of the covering layer being interposed between the first pillar upper surfaces and the capacitor cell dielectric layer; providing a conductive capacitor cell layer atop the capacitor cell dielectric layer to define an array of memory cell capacitors; providing an overlying layer of insulating material over the conductive capacitor cell layer; providing bit line contact openings through the overlying layer, conductive capacitor cell layer, cell capacitor dielectric layer and covering layer to the first pillar upper surfaces, the bit line contact openings having sidewalls, the bit line contact opening sidewalls including exposed edges of the conductive capacitor cell layer; electrically insulating exposed edges of the conductive capacitor cell layer within the bit line contact openings; and after electrically insulating the exposed edges, providing a digit line layer of conductive material atop the wafer and within the bit line contact openings, the digit line layer electrically connecting with the first pillar upper surfaces.