US5389568A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of making a dynamic random access memory device
Assignee: Samsung Electronics Co Ltd
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Filing: 1993-10-29
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Granted: 1995-02-14
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Expires: 2013-10-29
Abstract
Abstract Disclosed is a dynamic random access memory device (DRAM) having an increased cell capacitance and simplified manufacturing method thereof. The storage electrode the capacitor of the DRAM is connected to a semiconductor substrate through an opening formed in an insulating layer, and has a structure having an outer peripheral wall portion with a laterally extending bottom on the insulating layer and an inner central pillar portion including a hole of a certain depth within the opening in the center of the outer peripheral wall portion. Thus, cell capacitance is greatly increased within a limited unit cell area, its reliability is enhanced, and the manufacturing process is distinctly simplified.
Inventors
- 👤 Joo-young Yun
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 18:04
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10B12/0335; H10D; H10D1/00; H10D1/01; H10D1/041; H10D1/042; H10B12/30; H10B12/31; H10B12/318; H10D1/043; H10D1/60; H10D1/68; H10D1/692; H10D1/696; H10D1/711; H10D1/716
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
167 words
A method of manufacturing a capacitor electrode in a semiconductor device comprising the steps of: (a) forming an insulating layer on a semiconductor substrate having at least one transistor with a source region; (b) forming a first conductive layer on said insulating layer; (c) forming at least one first material pattern on said first conductive layer corresponding in location to said source region; (d) etching said at least one first material pattern, said first conductive layer, and said insulating layer to form a first opening which exposes said source region; (e) forming a second conductive layer over said first conductive layer having said opening formed therethrough, said second conductive layer covering a sidewall of said first opening and said source region to obtain a second opening having a smaller diameter than said first opening; (f) etching back said second conductive layer to expose said at least one etched first material pattern; and (g) removing said at least one etched first material pattern to obtain said capacitor electrode.
Claim 2
Independent Claim
167 words
A method of manufacturing a capacitor electrode in a semiconductor device comprising the steps of: (a) forming an insulating layer on a semiconductor substrate having at least one transistor with a source region; (b) forming a first conductive layer on said insulating layer; (c) forming at least one first material pattern on said first conductive layer corresponding in location to said source region; (d) etching said at least one first material pattern, said first conductive layer, and said insulating layer to form a first opening which exposes said source region; (e) forming a second conductive layer over said first conductive layer having said opening formed therethrough, said second conductive layer covering a sidewall of said first opening and said source region to obtain a second opening having a smaller diameter than said first opening; (f) etching back said second conductive layer to expose said at least one etched first material pattern; and (g) removing said at least one etched first material pattern to obtain said capacitor electrode.
Claim 3
Dependent Claim
32 words
A method of manufacturing a capacitor electrode as claimed in claim 1, wherein said steps of forming said first and second conductive layers comprises forming first and second polycrystalline silicon layers, respectively.
Claim 4
Dependent Claim
45 words
A method of manufacturing a capacitor electrode as claimed in claim 1, wherein said step of forming at least one first material pattern comprises the steps of forming a first material layer on said first conductive layer and patterning said first material layer by photolithography.
Claim 5
Dependent Claim
45 words
A method of manufacturing a capacitor electrode as claimed in claim 1, wherein said step of forming at least one first material pattern comprises the steps of forming a compound material layer on said first conductive layer and patterning said compound material layer by photolithography.
Claim 6
Dependent Claim
33 words
A method of manufacturing a capacitor electrode as claimed in claim 1, further comprising a step of forming a second material layer on said insulating layer, prior to forming said first conductive layer.
Claim 7
Dependent Claim
57 words
A method of manufacturing a capacitor electrode as claimed in claim 5, further comprising a step of etching back said second material layer formed on said insulating layer after said step of removing said at least one etched first material pattern, thereby leaving a lower surface portion of said capacitor electrode spaced away from said insulating layer.
Claim 8
Dependent Claim
28 words
A method of manufacturing a capacitor electrode as claimed in claim 1, wherein said step of forming said second conductive layer causes said second opening to be formed.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-02-13 | 1998-08-15 | 1999-02-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-02-13 | 2002-08-15 | 2003-02-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-02-13 | 2006-08-15 | 2007-02-14 | $7700.00 | Window Closed / Lapsed |