Double capacitor and manufacturing method thereof

Claim 2

A double capacitor for a semiconductor integrated circuit capable of being connected to another circuit element comprising: a first capacitor comprising: a first conductor formed in a substrate below and alongside a recess formed on one side of said substrate, a first non-conductor disposed over said first conductor, and a common ground conductor having a "U" shape disposed over said first non-conductor and within said recess and having free ends extending beyond said recess; and a second capacitor comprising: said common ground conductor, a second generally M-shaped non-conductor disposed over said common ground conductor, and a second conductor disposed over said second non-conductor.

Claim 3

A double capacitor according to claim 1 wherein said first and second capacitors are connected in parallel.

Claim 4

A double capacitor according to claim 1, wherein said first and second non-conductors are composed of an oxide layer having at least one of a NO and an ONO structure.

Claim 5

The double capacitor according to claim 1, wherein said first and second non-conductors have a thickness between 60 and 180 Å.

Claim 6

The double capacitor according to claim 1 wherein said first conductor includes a surface of said one side of said substrate doped to contain a depletion region.

Claim 7

The double capacitor according to claim 5, wherein said first conductor includes a dopant doped region of the same conductivity type as that of said depletion region below said recess.

Claim 8

The double capacitor according to claim 1 wherein said common ground conductor is composed of one of tungsten, titanium, and an alloy of one of said tungsten and titanium.

Claim 9

The double capacitor according to claim 1 wherein the thickness of said common ground conductor is 60-180 Å.

Claim 10

The double capacitor according to claim 1 wherein the thickness of said second conductor is substantially 2000 Å and is made of polycrystal silicon.

Claim 11

A manufacturing method for a double capacitor comprising the steps of: etching a portion of a substrate of a predetermined thickness to obtain a recessed area on one side of said substrate; depositing an oxide layer over said substrate to form a first non-conductor; diffusing a dopant through said recess into said substrate to form a first conductor; forming a common ground conductor having substantially a U shape within said recess; depositing a second oxide layer over said common ground conductor to form a second non-conductor; etching a portion of said first and second non-conductors to provide a connecting area to said first conductor; depositing a conductive dopant over said second non-conductor and within said connecting area to form a second conductor electrically connected to said first conductor.

Claim 12

A manufacturing method for a double capacitor comprising the steps of: etching a portion of a substrate of a predetermined thickness to obtain a recessed area on one side of said substrate; depositing an oxide layer over said substrate to form a first non-conductor; diffusing a dopant through said recess into said substrate to form a first conductor; forming a common ground conductor having substantially a U shape within said recess; depositing a second oxide layer over said common ground conductor to form a second non-conductor; etching a portion of said first and second non-conductors to provide a connecting area to said first conductor; depositing a conductive dopant over said second non-conductor and within said connecting area to form a second conductor electrically connected to said first conductor.

Claim 13

A method according to claim 10 further including the step of diffusing said one side of said substrate with a predetermined dopant to form a depletion region that serves as a part of said first conductor.

Claim 14

A method according to claim 1, wherein said diffusing step diffuses said dopant partially into said depletion region alongside said recess.

Claim 15

A method according to claim 10 wherein said common ground conductor forming step comprises the steps of: depositing a tri-layer structure comprising a first photoresistive bottom layer, a metal middle layer, and a second photoresistive upper layer over said first conductor; etching away a portion of said tri-layer structure to provide a tri-layer mask; and depositing a metal using said tri-layer mask to form said common ground conductor.

Claim 16

A manufacturing method according to claim 13 wherein said metal depositing step uses sputtering.

Claim 17

A manufacturing method according to claim 13 wherein said metal depositing step uses isotropic sputtering.

Claim 18

A method according to claim 13 further comprising the steps of: irradiating said tri-layer mask with ultraviolet rays after depositing said metal to facilitate removal of said mask; and removing said tri-layer mask.

Claim 19

A method according to claim 13 further comprising the steps of: baking said tri-layer mask after depositing said metal to facilitate removal of said mask; and removing said tri-layer mask.