US4702937A
Expired / Lapsed
US
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Method for manufacturing a semiconductor device
Assignee: Sony Corp
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Filing: 1985-12-03
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Granted: 1987-10-27
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Expires: 2005-12-03
Abstract
Abstract The invention relates to a method for manufacturing a semiconductor device with a resistor having a high resistance. In the invention, a first polycrystalline silicon layer is first formed to connect with an electrically connecting portion formed in a semiconductor substrate. Next, a second polycrystalline silicon layer containing oxygen is formed on the first polycrystalline silicon layer. And then, an oxide formed between the two polycrystalline silicon layer is removed by annealing.
Inventors
- 👤 Hisayoshi Yamoto
- 👤 Hideo Suzuki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 22:57
CPC Classifications
H; H10; H10B; H10B10/00; H10B10/15; H10D; H10D1/00; H10D1/40; H10D1/47; H10P; H10P95/00; H10P95/90; Y; Y10; Y10S; Y10S257/00; Y10S257/903; Y10S257/904
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
99 words
The method of manufacturing a semiconductor device incorporating a polycrystalline layer containing oxygen, comprising the steps of: forming a first polycrystalline silicon layer over at least an electrically connecting portion formed in a semiconductor substrate; forming a second polycrystalline silicon layer, containing oxygen, on said first polycrystalline silicon layer and thereby forming a layer of silicon dioxide between the first and second layers; and annealing said semiconductor substrate on which said first and second polycrystalline silicon layers are formed thereby converting the silicon dioxide layer into discontinuous SiO 2 masses and substantially ohmically connecting said first and second layers.
Claim 2
Independent Claim
99 words
The method of manufacturing a semiconductor device incorporating a polycrystalline layer containing oxygen, comprising the steps of: forming a first polycrystalline silicon layer over at least an electrically connecting portion formed in a semiconductor substrate; forming a second polycrystalline silicon layer, containing oxygen, on said first polycrystalline silicon layer and thereby forming a layer of silicon dioxide between the first and second layers; and annealing said semiconductor substrate on which said first and second polycrystalline silicon layers are formed thereby converting the silicon dioxide layer into discontinuous SiO 2 masses and substantially ohmically connecting said first and second layers.
Claim 3
Dependent Claim
21 words
A method according to claim 1, wherein said electrically connecting portion is an impurity diffusion region formed in said semiconductor substrate.
Claim 4
Dependent Claim
24 words
A method according to claim 1, wherein said first and second polycrystalline silicon layers are formed over generally the region of said semiconductor substrate,
Claim 5
Dependent Claim
24 words
A method according to claim 1, wherein said first polycrystalline silicon layer is formed in a limited area only near said electrically connecting portion.
Claim 6
Dependent Claim
20 words
A method according to claim 4, wherein said first polycrystalline silicon layer has a thickness of 1,000 to 2,000 Å.
Claim 7
Dependent Claim
29 words
A method according to claim 5, wherein said second polycrystalline silicon layer contains 2 to 10 atomic % of oxygen and is larger in area than said first layer.
Claim 8
Dependent Claim
26 words
A method according to claim 6, wherein the annealing step is performed in a nitrogen atmosphere at 900° to 1,000° C. for 20 to 60 minutes.
Claim 9
Dependent Claim
34 words
A method according to claim 1, wherein said first polycrystalline silicon layer has a thickness of 50 to 200 A, and said second polycrystalline silicon layer has a thickness of 1,500 to 4,000 Å.
Claim 10
Dependent Claim
20 words
A method according to claim 8, wherein said second polycrystalline silicon layer contains 2 to 10 atomic % of oxygen.
Claim 11
Dependent Claim
26 words
A method according to claim 9, wherein the annealing step is performed in a nitrogen atmosphere at 900° to 1,000° C. for 20 to 60 minutes.
Claim 12
Dependent Claim
26 words
A method according to claim 1, wherein the annealing step is performed in a nitrogen atmosphere at 900° to 1,000° C. for 20 to 60 minutes.
Claim 13
Dependent Claim
21 words
A method according to claim 1, wherein said first and second polycrystalline silicon layers serve as a resistor of an SRAM.
Claim 14
Dependent Claim
21 words
A method according to claim 12, wherein said electrically connecting portion is a drain region of an FET of said SRAM.
Claim 15
Dependent Claim
20 words
A method according to claim 1, wherein said second polycrystalline silicon layer contains 2 to 10 atomic 5 of oxygen.
Claim 16
Independent Claim
98 words
The method of manufacturing a semiconductor device comprising the steps of: forming a first polycrystalline silicon layer over at least an electrically connecting portion formed in a semiconductor substrate; forming a second polycrystalline silicon layer, containing oxygen, on said first polycrystalline silicon layer, and thereby providing a thin layer of SiO 2 between said first and second layer; and annealing said semiconductor substrate on which said first and second polycrystalline silicon layers are formed, causing silicon crystalline growth in said first and second layers dispersing the SiO 2 of said thin layer to substantially ohmically connect said layers.
Claim 17
Independent Claim
98 words
The method of manufacturing a semiconductor device comprising the steps of: forming a first polycrystalline silicon layer over at least an electrically connecting portion formed in a semiconductor substrate; forming a second polycrystalline silicon layer, containing oxygen, on said first polycrystalline silicon layer, and thereby providing a thin layer of SiO 2 between said first and second layer; and annealing said semiconductor substrate on which said first and second polycrystalline silicon layers are formed, causing silicon crystalline growth in said first and second layers dispersing the SiO 2 of said thin layer to substantially ohmically connect said layers.
References Cited (Backward Citations)
US4087571A
Cited
US4489103A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1990-10-26 | 1991-04-27 | 1991-10-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-10-26 | 1995-04-27 | 1995-10-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-10-26 | 1999-04-27 | 1999-10-27 | $7700.00 | Window Closed / Lapsed |