US5361234A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory cell device having dummy capacitors reducing boundary level changes between a memory cell array area and a peripheral circuit area
Assignee: Micron Memory Japan Ltd
•
Filing: 1993-03-26
•
Granted: 1994-11-01
•
Expires: 2013-03-26
Abstract
Abstract A semiconductor memory device comprises a plurality of word lines, a plurality of digit lines, a peripheral circuit area and a memory cell array area. The memory cell array area comprises a semiconductor substrate having a surface in which field oxide films are selectively formed, a plurality of operational memory cells arrayed on active regions within the memory cell array area, each of which includes a stacked capacitor and a switching transistor, and a plurality of dummy capacitors arranged within the memory cell array area at an adjacent portion to a boundary area between the memory cell array area and the peripheral circuit area. The dummy capacitor is to receive affections caused by an inferiority of the accuracy of patterning by a photolithography in replacement of the operational memory cells. The dummy capacitor is so formed over the field oxide film as to prevent said digit line at said boundary area to have a rapid slope or a large difference in level.
Inventors
- 👤 Shinya Iwasa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 18:57
CPC Classifications
H; H10; H10B; H10B12/00
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
166 words
A semiconductor memory device comprising: a plurality of word lines; a plurality of digit lines; a peripheral circuit area; and a memory cell array area comprising: a semiconductor substrate having a surface in which field oxide films are selectively formed; a plurality of operational memory cells arrayed on active regions within said memory cell array area, each of said memory cells including a stacked capacitor and a switching transistor; and a plurality of dummy capacitors arranged in a boundary area between said memory cell array area and said peripheral circuit area, said dummy capacitors each comprising a pair of electrode layers and an intermediate insulation layer, each of said pair of electrode layers and said intermediate insulation layers comprising side portions proximate said peripheral circuit area and opposite side portions proximate said memory cell array area, wherein at least said side portions of said electrode layers and insulation layers proximate said peripheral circuit area overlie said field oxide films without overlying any of said word lines.
Claim 2
Dependent Claim
166 words
A semiconductor memory device comprising: a plurality of word lines; a plurality of digit lines; a peripheral circuit area; and a memory cell array area comprising: a semiconductor substrate having a surface in which field oxide films are selectively formed; a plurality of operational memory cells arrayed on active regions within said memory cell array area, each of said memory cells including a stacked capacitor and a switching transistor; and a plurality of dummy capacitors arranged in a boundary area between said memory cell array area and said peripheral circuit area, said dummy capacitors each comprising a pair of electrode layers and an intermediate insulation layer, each of said pair of electrode layers and said intermediate insulation layers comprising side portions proximate said peripheral circuit area and opposite side portions proximate said memory cell array area, wherein at least said side portions of said electrode layers and insulation layers proximate said peripheral circuit area overlie said field oxide films without overlying any of said word lines.
Claim 3
Dependent Claim
27 words
The semiconductor memory device as claimed in claim 1, wherein said dummy capacitors overlie said semiconductor substrate without any portion thereof overlying any of said word lines.
Claim 4
Dependent Claim
25 words
The semiconductor memory device as claimed in claim 2, wherein said dummy capacitors and said stacked capacitors are concurrently formed in the same fabrication process.
Claim 5
Dependent Claim
59 words
The semiconductor memory device as claimed in claim 1, further comprising dummy word lines underlying said opposite side portions of said pair of electrode layers and said intermediate insulation layers of said dummy capacitors, whereby said dummy capacitors slope downwardly from said opposite portions proximate said memory cell array area to said side portions proximate said peripheral circuit area.
Claim 6
Dependent Claim
43 words
The semiconductor memory device as claimed in claim 4, wherein said dummy capacitors and said stacked capacitors are concurrently formed in the same fabrication process, and wherein said dummy word lines and said operational word lines are concurrently formed in the same process.
References Cited (Backward Citations)
JPH0499375A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-10-31 | 1998-05-02 | 1998-11-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-10-31 | 2002-05-02 | 2002-11-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-10-31 | 2006-05-02 | 2006-11-01 | $7700.00 | Window Closed / Lapsed |