High-frequency wireless communication system on a single ultrathin silicon on sapphire chip

Claim 2

A transistor comprising: an electrically insulating substrate having a first surface; and a layer of silicon formed on said first surface of said electrically insulating substrate, wherein: said layer of silicon has an areal density of electrically active states in regions not intentionally doped which is less than approximately 5×10 11 cm -2 achieved by performing any processing of said silicon layer which subjects the silicon layer to temperatures in excess of approximately 950° C. in an oxidizing ambient environment; and said layer of silicon has a thickness which is less than approximately 270 nm.

Claim 3

A transistor as defined in claim 1 wherein said transistor further comprises a field-effect-transistor (FET).

Claim 4

A transistor as defined in claim 1 wherein said electrically insulating substrate further comprises sapphire.

Claim 5

A MOSFET comprising: a sapphire substrate; and a layer of silicon deposited on said sapphire substrate, said layer of silicon having an areal density of electrically active states in regions not intentionally doped which is less than approximately 5×10 11 cm -2 achieved by performing any processing of said layer of silicon which subjects said layer of silicon to temperatures in excess of approximately 950° C. in an oxidizing ambient environment, wherein said layer of silicon further comprises: a source region; a drain region; and a channel region, wherein said channel region is less than approximately 270 nm thick and has an areal density of electrically active states in regions which are not intentionally doped which is less than approximately 5×10 11 cm -2 thereby capable of being fully depleted.

Claim 6

A MOSFET comprising: a sapphire substrate; and a layer of silicon deposited on said sapphire substrate, said layer of silicon having an areal density of electrically active states in regions not intentionally doped which is less than approximately 5×10 11 cm -2 achieved by performing any processing of said layer of silicon which subjects said layer of silicon to temperatures in excess of approximately 950° C. in an oxidizing ambient environment, wherein said layer of silicon further comprises: a source region; a drain region; and a channel region, wherein said channel region is less than approximately 270 nm thick and has an areal density of electrically active states in regions which are not intentionally doped which is less than approximately 5×10 11 cm -2 thereby capable of being fully depleted.

Claim 7

A MOSFET as defined in claim 4 wherein said source region further comprises dopant atoms.

Claim 8

A MOSFET as defined in claim 4 wherein said drain region further comprises dopant atoms.

Claim 9

A MOSFET as defined in claim 4 wherein said channel region further comprises dopant atoms in a concentration which has a lower limit which is sufficient to induce surface channel conduction and an upper limit which does not prevent full depletion of said channel region.

Claim 10

A MOSFET as defined in claim 4 further comprising a gate dielectric layer adjacent said channel region and a gate conductor layer adjacent said gate dielectric layer.

Claim 11

A MOSFET as defined in claim 8 wherein said gate conductor layer further comprises N + polysilicon in contact with said gate dielectric layer.

Claim 12

A MOSFET as defined in claim 8 wherein said gate conductor layer further comprises P + polysilicon in contact with said gate dielectric layer.

Claim 13

A MOSFET as defined in claim 8 wherein said gate conductor layer further comprises a material having a metal work function which is in the range of from 4.5 eV to 4.7 eV.

Claim 14

A MOSFET as defined in claim 11 wherein said material having a metal work function which is in the range of from 4.5 eV to 4.7 eV is selected from a group of materials which includes P + polygermanium, tungsten, chromium, indium tin oxide and titanium nitride.

Claim 15

A MOSFET as defined in claim 8 further comprising a sidewall spacer adjacent said gate dielectric layer and adjacent said gate conductor layer.

Claim 16

A MOSFET as defined in claim 4 wherein said source region further comprises a lightly doped source region.

Claim 17

A MOSFET as defined in claim 4 wherein said drain region further comprises a lightly doped drain region.

Claim 18

A MOSFET as defined in claim 4 wherein said channel region is intentionally doped to adjust threshold voltage.

Claim 19

A transistor formed in a silicon layer which is formed on a sapphire substrate wherein said silicon layer is less than approximately 270 nm thick and has an areal density of electrically active states in regions not intentionally doped which is less than approximately 5×10 11 cm -2 , said transistor produced by the process comprising the steps of: epitaxially depositing a layer of silicon on a surface of a sapphire substrate; implanting a given ion species into said layer of silicon under such conditions that said implanted ions form a buried amorphous region in said silicon layer which extends substantially from said surface of said sapphire substrate into said layer of silicon, thus leaving a surface layer of monocrystalline silicon covering said buried amorphous region; annealing the wafer to induce solid phase epitaxial regrowth of said buried amorphous region using said surface layer of monocrystalline silicon as a crystallization seed; and performing all processing of said layer of silicon subsequent to said ion implanting step which subject said layer of silicon to temperatures in excess of approximately 950° C. in an oxidizing ambient environment, thereby maintaining an areal density of electrically active states in regions of the silicon not intentionally doped which is less than approximately 5×10 11 cm -2 .

Claim 20

A transistor formed in a silicon layer which is formed on a sapphire substrate wherein said silicon layer is less than approximately 270 nm thick and has an areal density of electrically active states in regions not intentionally doped which is less than approximately 5×10 11 cm -2 , said transistor produced by the process comprising the steps of: epitaxially depositing a layer of silicon on a surface of a sapphire substrate; implanting a given ion species into said layer of silicon under such conditions that said implanted ions form a buried amorphous region in said silicon layer which extends substantially from said surface of said sapphire substrate into said layer of silicon, thus leaving a surface layer of monocrystalline silicon covering said buried amorphous region; annealing the wafer to induce solid phase epitaxial regrowth of said buried amorphous region using said surface layer of monocrystalline silicon as a crystallization seed; and performing all processing of said layer of silicon subsequent to said ion implanting step which subject said layer of silicon to temperatures in excess of approximately 950° C. in an oxidizing ambient environment, thereby maintaining an areal density of electrically active states in regions of the silicon not intentionally doped which is less than approximately 5×10 11 cm -2 .

Claim 21

A transistor produced by the process defined in claim 17 further comprising the step of: maintaining said layer of silicon during formation of said buried amorphous region at or below a predetermined temperature which is substantially uniform throughout said layer of silicon during said ion implanting step.

Claim 22

A transistor produced by the process defined in claim 18 wherein said predetermined temperature of said layer of silicon during formation of said buried amorphous region is maintained at approximately zero degrees centigrade (0° C.).

Claim 23

A transistor produced by the process defined in claim 17 further comprising the step of forming a channel region in said layer of silicon which is intentionally doped to adjust a threshold voltage of said transistor.

Claim 24

A transistor produced by the process defined in claim 17 wherein said transistor is a MOSFET.

Claim 25

A transistor comprising: an electrically insulating substrate having a first surface; and a layer of silicon formed on said first surface of said electrically insulating substrate, wherein said layer of silicon has an areal density of electrically active states in regions not intentionally doped which is less than approximately 5×10 11 cm -2 achieved by adhering to the following processing criteria: 1) performing any processing of said layer of silicon which subjects said layer of silicon to temperatures in excess of approximately 950° C. in an oxidizing ambient environment; and 2) performing any processing of said layer of silicon which subjects said layer of silicon to temperatures which are less than approximately 950° C. in either one of an oxidizing ambient environment or a non-oxidizing ambient environment.

Claim 26

A transistor comprising: an electrically insulating substrate having a first surface; and a layer of silicon formed on said first surface of said electrically insulating substrate, wherein said layer of silicon has an areal density of electrically active states in regions not intentionally doped which is less than approximately 5×10 11 cm -2 achieved by adhering to the following processing criteria: 1) performing any processing of said layer of silicon which subjects said layer of silicon to temperatures in excess of approximately 950° C. in an oxidizing ambient environment; and 2) performing any processing of said layer of silicon which subjects said layer of silicon to temperatures which are less than approximately 950° C. in either one of an oxidizing ambient environment or a non-oxidizing ambient environment.

Claim 27

A transistor as defined in claim 22 wherein said transistor further comprises a field-effect-transistor (FET).

Claim 28

A transistor as defined in claim 22 wherein said electrically insulating substrate further comprises sapphire.

Claim 29

A transistor formed in a silicon layer which is formed on a sapphire substrate wherein said silicon layer is less than approximately 270 nm thick and has an areal density of electrically active states in regions not intentionally doped which is less than approximately 5×10 11 cm -2 ,said transistor produced by the process comprising the steps of: epitaxially depositing a layer of silicon on a surface of a sapphire substrate; implanting a given ion species into said layer of silicon under such conditions that said implanted ions form a buried amorphous region in said silicon layer which extends substantially from said surface of said sapphire substrate into said layer of silicon, thus leaving a surface layer of monocrystalline silicon covering said buried amorphous region; selecting an areal portion of said layer of silicon and maintaining said areal portion of said layer of silicon during formation of said buried amorphous region at or below a predetermined temperature which is substantially uniform throughout said areal portion of said layer of silicon during said ion implanting step; annealing the wafer to induce solid phase epitaxial regrowth of said buried amorphous region using said surface layer of monocrystalline silicon as a crystallization seed; performing any processing of said layer of silicon which subjects said layer of silicon to temperatures in excess of approximately 950° C. in an oxidizing ambient environment; and performing any processing of said layer of silicon which subjects said layer of silicon to temperatures which are less than approximately 950° C. in either one of an oxidizing ambient environment or a non-oxidizing ambient environment.

Claim 30

A transistor formed in a silicon layer which is formed on a sapphire substrate wherein said silicon layer is less than approximately 270 nm thick and has an areal density of electrically active states in regions not intentionally doped which is less than approximately 5×10 11 cm -2 ,said transistor produced by the process comprising the steps of: epitaxially depositing a layer of silicon on a surface of a sapphire substrate; implanting a given ion species into said layer of silicon under such conditions that said implanted ions form a buried amorphous region in said silicon layer which extends substantially from said surface of said sapphire substrate into said layer of silicon, thus leaving a surface layer of monocrystalline silicon covering said buried amorphous region; selecting an areal portion of said layer of silicon and maintaining said areal portion of said layer of silicon during formation of said buried amorphous region at or below a predetermined temperature which is substantially uniform throughout said areal portion of said layer of silicon during said ion implanting step; annealing the wafer to induce solid phase epitaxial regrowth of said buried amorphous region using said surface layer of monocrystalline silicon as a crystallization seed; performing any processing of said layer of silicon which subjects said layer of silicon to temperatures in excess of approximately 950° C. in an oxidizing ambient environment; and performing any processing of said layer of silicon which subjects said layer of silicon to temperatures which are less than approximately 950° C. in either one of an oxidizing ambient environment or a non-oxidizing ambient environment.

Claim 31

A MOSFET comprising: a sapphire substrate; and a layer of silicon deposited on said sapphire substrate, said layer of silicon having an areal density of electrically active states in regions not intentionally doped which is less than approximately 5×10 11 cm -2 achieved by adhering to the following processing criteria: 1) performing any processing of said layer of silicon which subjects said layer of silicon to temperatures in excess of approximately 950° C. in an oxidizing ambient environment; and 2) performing any processing of said layer of silicon which subjects said layer of silicon to temperatures which are less than approximately 950° C. in either one of an oxidizing ambient environment or a non-oxidizing ambient environment, wherein said layer of silicon further comprises: a source region; a drain region; and a channel region, wherein said channel region is less than approximately 270 nm thick and has an areal density of electrically active states in regions which are not intentionally doped which is less than approximately 5×10 11 cm -2 thereby capable of being fully depleted.

Claim 32

A MOSFET comprising: a sapphire substrate; and a layer of silicon deposited on said sapphire substrate, said layer of silicon having an areal density of electrically active states in regions not intentionally doped which is less than approximately 5×10 11 cm -2 achieved by adhering to the following processing criteria: 1) performing any processing of said layer of silicon which subjects said layer of silicon to temperatures in excess of approximately 950° C. in an oxidizing ambient environment; and 2) performing any processing of said layer of silicon which subjects said layer of silicon to temperatures which are less than approximately 950° C. in either one of an oxidizing ambient environment or a non-oxidizing ambient environment, wherein said layer of silicon further comprises: a source region; a drain region; and a channel region, wherein said channel region is less than approximately 270 nm thick and has an areal density of electrically active states in regions which are not intentionally doped which is less than approximately 5×10 11 cm -2 thereby capable of being fully depleted.

Claim 33

A MOSFET as defined in claim 26 wherein said source region further comprises dopant atoms.

Claim 34

A MOSFET as defined in claim 26 wherein said drain region further comprises dopant atoms.

Claim 35

A MOSFET as defined in claim 26 wherein said channel region further comprises dopant atoms in a concentration which has a lower limit which is sufficient to induce surface channel conduction and an upper limit which does not prevent full depletion of said channel region.

Claim 36

A MOSFET as defined in claim 26 further comprising a gate dielectric layer adjacent said channel region and a gate conductor layer adjacent said gate dielectric layer.

Claim 37

A MOSFET as defined in claim 30 wherein said gate conductor layer further comprises N + polysilicon in contact with said gate dielectric layer.

Claim 38

A MOSFET as defined in claim 30 wherein said gate conductor layer further comprises P + polysilicon in contact with said gate dielectric layer.

Claim 39

A MOSFET as defined in claim 30 wherein said gate conductor layer further comprises a material having a metal work function which is in the range of from 4.5 eV to 4.7 eV.

Claim 40

A MOSFET as defined in claim 33 wherein said material having a metal work function which is in the range of from 4.5 eV to 4.7 eV is selected from a group of materials which includes P + polygermanium, tungsten, chromium, indium tin oxide and titanium nitride.

Claim 41

A MOSFET as defined in claim 30 further comprising a sidewall spacer adjacent said gate dielectric layer and adjacent said gate conductor layer.

Claim 42

A MOSFET as defined in claim 26 wherein said source region further comprises a lightly doped source region.

Claim 43

A MOSFET as defined in claim 26 wherein said drain region further comprises a lightly doped drain region.

Claim 44

A MOSFET as defined in claim 26 wherein said channel region is intentionally doped to adjust threshold voltage.

Claim 45

A transistor formed in a silicon layer which is formed on a sapphire substrate wherein said silicon layer is less than approximately 270 nm thick and has an areal density of electrically active states in regions not intentionally doped which is less than approximately 5×10 11 cm -2 , said transistor produced by the process comprising the steps of: epitaxially depositing a layer of silicon on a surface of a sapphire substrate; implanting a given ion species into said layer of silicon under such conditions that said implanted ions form a buried amorphous region in said silicon layer which extends substantially from said surface of said sapphire substrate into said layer of silicon, thus leaving a surface layer of monocrystalline silicon covering said buried amorphous region; annealing the wafer to induce solid phase epitaxial regrowth of said buried amorphous region using said surface layer of monocrystalline silicon as a crystallization seed; performing any processing of said layer of silicon which subjects said layer of silicon to temperatures in excess of approximately 950° C. in an oxidizing ambient environment; and performing any processing of said layer of silicon which subjects said layer of silicon to temperatures which are less than approximately 950° C. in either one of an oxidizing ambient environment or a non-oxidizing ambient environment.

Claim 46

A transistor formed in a silicon layer which is formed on a sapphire substrate wherein said silicon layer is less than approximately 270 nm thick and has an areal density of electrically active states in regions not intentionally doped which is less than approximately 5×10 11 cm -2 , said transistor produced by the process comprising the steps of: epitaxially depositing a layer of silicon on a surface of a sapphire substrate; implanting a given ion species into said layer of silicon under such conditions that said implanted ions form a buried amorphous region in said silicon layer which extends substantially from said surface of said sapphire substrate into said layer of silicon, thus leaving a surface layer of monocrystalline silicon covering said buried amorphous region; annealing the wafer to induce solid phase epitaxial regrowth of said buried amorphous region using said surface layer of monocrystalline silicon as a crystallization seed; performing any processing of said layer of silicon which subjects said layer of silicon to temperatures in excess of approximately 950° C. in an oxidizing ambient environment; and performing any processing of said layer of silicon which subjects said layer of silicon to temperatures which are less than approximately 950° C. in either one of an oxidizing ambient environment or a non-oxidizing ambient environment.

Claim 47

A transistor produced by the process defined in claim 39 further comprising the step of: maintaining said layer of silicon during formation of said buried amorphous region at or below a predetermined temperature which is substantially uniform throughout said layer of silicon during said ion implanting step.

Claim 48

A transistor produced by the process defined in claim 40 wherein said predetermined temperature of said layer of silicon during formation of said buried amorphous region is maintained at approximately zero degrees centigrade (0° C.).

Claim 49

A transistor produced by the process defined in claim 39 further comprising the step of forming a channel region in said layer of silicon which is intentionally doped to adjust a threshold voltage of said transistor.

Claim 50

A transistor produced by the process defined in claim 39 wherein said transistor is a MOSFET.

Claim 51

A transistor comprising: an electrically insulating substrate having a first surface; and a layer of silicon formed on said first surface of said electrically insulating substrate, wherein: said layer of silicon has an areal density of electrically active states in regions not intentionally doped which is less than approximately 5×10 11 cm -2 achieved by performing any processing of said silicon layer which exposes said silicon layer to a non-oxidizing ambient environment at temperatures of less than or equal to approximately 950° C.; and said layer of silicon has a thickness which is less than approximately 270 nm.

Claim 52

A transistor comprising: an electrically insulating substrate having a first surface; and a layer of silicon formed on said first surface of said electrically insulating substrate, wherein: said layer of silicon has an areal density of electrically active states in regions not intentionally doped which is less than approximately 5×10 11 cm -2 achieved by performing any processing of said silicon layer which exposes said silicon layer to a non-oxidizing ambient environment at temperatures of less than or equal to approximately 950° C.; and said layer of silicon has a thickness which is less than approximately 270 nm.

Claim 53

A transistor as defined in claim 44 wherein said transistor further comprises a field-effect-transistor (FET).

Claim 54

A transistor as defined in claim 44 wherein said electrically insulating substrate further comprises sapphire.

Claim 55

A transistor formed in a silicon layer which is formed on a sapphire substrate wherein said silicon layer is less than approximately 270 nm thick and has an areal density of electrically active states in regions not intentionally doped which is less than approximately 5×10 11 cm -2 , said transistor produced by the process comprising the steps of: epitaxially depositing a layer of silicon on a surface of a sapphire substrate; implanting a given ion species into said layer of silicon under such conditions that said implanted ions form a buried amorphous region in said silicon layer which extends substantially from said surface of said sapphire substrate into said layer of silicon, thus leaving a surface layer of monocrystalline silicon covering said buried amorphous region; selecting an areal portion of said layer of silicon and maintaining said areal portion of said layer of silicon during formation of said buried amorphous region at or below a predetermined temperature which is substantially uniform throughout said areal portion of said layer of silicon during said ion implanting step; annealing the wafer to induce solid phase epitaxial regrowth of said buried amorphous region using said surface layer of monocrystalline silicon as a crystallization seed; and performing all annealing and/or processing procedures which expose said layer of silicon to a non-oxidizing ambient environment at or below a temperature of approximately 950° C., thereby maintaining an areal density of electrically active states in regions of the silicon not intentionally doped which is less than approximately 5×10 11 cm -2 .

Claim 56

A transistor formed in a silicon layer which is formed on a sapphire substrate wherein said silicon layer is less than approximately 270 nm thick and has an areal density of electrically active states in regions not intentionally doped which is less than approximately 5×10 11 cm -2 , said transistor produced by the process comprising the steps of: epitaxially depositing a layer of silicon on a surface of a sapphire substrate; implanting a given ion species into said layer of silicon under such conditions that said implanted ions form a buried amorphous region in said silicon layer which extends substantially from said surface of said sapphire substrate into said layer of silicon, thus leaving a surface layer of monocrystalline silicon covering said buried amorphous region; selecting an areal portion of said layer of silicon and maintaining said areal portion of said layer of silicon during formation of said buried amorphous region at or below a predetermined temperature which is substantially uniform throughout said areal portion of said layer of silicon during said ion implanting step; annealing the wafer to induce solid phase epitaxial regrowth of said buried amorphous region using said surface layer of monocrystalline silicon as a crystallization seed; and performing all annealing and/or processing procedures which expose said layer of silicon to a non-oxidizing ambient environment at or below a temperature of approximately 950° C., thereby maintaining an areal density of electrically active states in regions of the silicon not intentionally doped which is less than approximately 5×10 11 cm -2 .

Claim 57

A MOSFET comprising: a sapphire substrate; and a layer of silicon deposited on said sapphire substrate, said layer of silicon having an areal density of electrically active states in regions not intentionally doped which is less than approximately 5×10 11 cm -2 achieved by performing any processing of said layer of silicon which exposes said layer of silicon to a non-oxidizing ambient environment at temperatures of less than or equal to approximately 950° C., wherein said layer of silicon further comprises: a source region; a drain region; and a channel region, wherein said channel region is less than approximately 270 nm thick and has an areal density of electrically active states in regions which are not intentionally doped which is less than approximately 5×10 11 cm -2 thereby capable of being fully depleted.

Claim 58

A MOSFET comprising: a sapphire substrate; and a layer of silicon deposited on said sapphire substrate, said layer of silicon having an areal density of electrically active states in regions not intentionally doped which is less than approximately 5×10 11 cm -2 achieved by performing any processing of said layer of silicon which exposes said layer of silicon to a non-oxidizing ambient environment at temperatures of less than or equal to approximately 950° C., wherein said layer of silicon further comprises: a source region; a drain region; and a channel region, wherein said channel region is less than approximately 270 nm thick and has an areal density of electrically active states in regions which are not intentionally doped which is less than approximately 5×10 11 cm -2 thereby capable of being fully depleted.

Claim 59

A MOSFET as defined in claim 48 wherein said source region further comprises dopant atoms.

Claim 60

A MOSFET as defined in claim 48 wherein said drain region further comprises dopant atoms.

Claim 61

A MOSFET as defined in claim 48 wherein said channel region further comprises dopant atoms in a concentration which has a lower limit which is sufficient to induce surface channel conduction and an upper limit which does not prevent full depletion of said channel region.

Claim 62

A MOSFET as defined in claim 48 further comprising a gate dielectric layer adjacent said channel region and a gate conductor layer adjacent said gate dielectric layer.

Claim 63

A MOSFET as defined in claim 52 wherein said gate conductor layer further comprises N + polysilicon in contact with said gate dielectric layer.

Claim 64

A MOSFET as defined in claim 52 wherein said gate conductor layer further comprises P + polysilicon in contact with said gate dielectric layer.

Claim 65

A MOSFET as defined in claim 52 wherein said gate conductor layer further comprises a material having a metal work function which is in the range of from 4.5 eV to 4.7 eV.

Claim 66

A MOSFET as defined in claim 55 wherein said material having a metal work function which is in the range of from 4.5 eV to 4.7 eV is selected from a group of materials which includes P + polygermanium, tungsten, chromium, indium tin oxide and titanium nitride.

Claim 67

A MOSFET as defined in claim 52 further comprising a sidewall spacer adjacent said gate dielectric layer and adjacent said gate conductor layer.

Claim 68

A MOSFET as defined in claim 48 wherein said source region further comprises a lightly doped source region.

Claim 69

A MOSFET as defined in claim 48 wherein said drain region further comprises a lightly doped drain region.

Claim 70

A MOSFET as defined in claim 48 wherein said channel region is intentionally doped to adjust threshold voltage.

Claim 71

A transistor formed in a silicon layer which is formed on a sapphire substrate wherein said silicon layer is less than approximately 270 nm thick and has an areal density of electrically active states in regions not intentionally doped which is less than approximately 5×10 11 cm -2 , said transistor produced by the process comprising the steps of: epitaxially depositing a layer of silicon on a surface of a sapphire substrate; implanting a given ion species into said layer of silicon under such conditions that said implanted ions form a buried amorphous region in said silicon layer which extends substantially from said surface of said sapphire substrate into said layer of silicon, thus leaving a surface layer of monocrystalline silicon covering said buried amorphous region; annealing the wafer to induce solid phase epitaxial regrowth of said buried amorphous region using said surface layer of monocrystalline silicon as a crystallization seed; and performing all annealing and/or processing procedures which expose said layer of silicon to a non-oxidizing ambient environment at or below a temperature of approximately 950° C., thereby maintaining an areal density of electrically active states in regions of the silicon not intentionally doped which is less than approximately 5×10 11 cm -2 .

Claim 72

A transistor formed in a silicon layer which is formed on a sapphire substrate wherein said silicon layer is less than approximately 270 nm thick and has an areal density of electrically active states in regions not intentionally doped which is less than approximately 5×10 11 cm -2 , said transistor produced by the process comprising the steps of: epitaxially depositing a layer of silicon on a surface of a sapphire substrate; implanting a given ion species into said layer of silicon under such conditions that said implanted ions form a buried amorphous region in said silicon layer which extends substantially from said surface of said sapphire substrate into said layer of silicon, thus leaving a surface layer of monocrystalline silicon covering said buried amorphous region; annealing the wafer to induce solid phase epitaxial regrowth of said buried amorphous region using said surface layer of monocrystalline silicon as a crystallization seed; and performing all annealing and/or processing procedures which expose said layer of silicon to a non-oxidizing ambient environment at or below a temperature of approximately 950° C., thereby maintaining an areal density of electrically active states in regions of the silicon not intentionally doped which is less than approximately 5×10 11 cm -2 .

Claim 73

A transistor produced by the process defined in claim 61 further comprising the step of: maintaining said layer of silicon during formation of said buried amorphous region at or below a predetermined temperature which is substantially uniform throughout said layer of silicon during said ion implanting step.

Claim 74

A transistor produced by the process defined in claim 62 wherein said predetermined temperature of said layer of silicon during formation of said buried amorphous region is maintained at approximately zero degrees centigrade (0° C.).

Claim 75

A transistor produced by the process defined in claim 61 further comprising the step of forming a channel region in said layer of silicon which is intentionally doped to adjust a threshold voltage of said transistor.

Claim 76

A transistor produced by the process defined in claim 61 wherein said transistor is a MOSFET.