US5285069A — Array of field effect transistors of different th…

Claim 1

Independent Claim 167 words

A semiconductor integrated circuit apparatus comprising: a basic cell region formed by arranging a plurality of basic cells, each of said plurality of basic cells including a plurality of MOS transistors, in longitudinal and transversal directions; each of said plurality of MOS transistors having source and drain section diffusive regions, implanted with impurities of a conductivity type opposite to that in said diffusive regions, formed on a semiconductor substrate, and a gate electrode formed on a channel region between said source and drain section diffusive regions through a gate insulating film; the semiconductor integrated circuit apparatus being constructed such that the source and drain section diffusive regions of a first one of said plurality of MOS transistors is deeply implanted with said impurities at a high concentration and a withstand voltage of a first PN-junction between the diffusive region and the substrate of the first MOS transistor is lower than that of a second PN-junction between the substrate and a diffusive region of a second MOS transistor.

Claim 2

Dependent Claim 167 words

A semiconductor integrated circuit apparatus comprising: a basic cell region formed by arranging a plurality of basic cells, each of said plurality of basic cells including a plurality of MOS transistors, in longitudinal and transversal directions; each of said plurality of MOS transistors having source and drain section diffusive regions, implanted with impurities of a conductivity type opposite to that in said diffusive regions, formed on a semiconductor substrate, and a gate electrode formed on a channel region between said source and drain section diffusive regions through a gate insulating film; the semiconductor integrated circuit apparatus being constructed such that the source and drain section diffusive regions of a first one of said plurality of MOS transistors is deeply implanted with said impurities at a high concentration and a withstand voltage of a first PN-junction between the diffusive region and the substrate of the first MOS transistor is lower than that of a second PN-junction between the substrate and a diffusive region of a second MOS transistor.

Claim 3

Dependent Claim 30 words

A semiconductor integrated circuit apparatus as claimed in claim 1, wherein said first PN-junction having the lower withstand voltage is used as a surge protecting element in a terminal section.

Claim 4

Dependent Claim 22 words

A semiconductor integrated circuit apparatus as claimed in claim 1, wherein said first PN-junction having the lower withstand voltage has Zener characteristics.

Claim 5

Dependent Claim 161 words

A static RAM formed on a semiconductor integrated circuit of a master slice type formed by arranging a plurality of basic cells, each of said plurality of basic cells composed of a P-channel type MOS transistor and an N-channel type MOS transistor, on the same semiconductor chip in longitudinal and transversal directions, said static RAM comprising: a first MOS transistor of a memory cell in which a pair of CMOS inverter circuits are connected to each other; a second MOS transistor for access which is connected to each of memory nodes and has a word line signal as a gate input, ions being implanted into a channel of at least one of said first and second MOS transistors to change operating characteristics of the memory cell so that an operating state of the memory cell is set to an initial state when a predetermined voltage is applied to the memory cell from a bit line through the MOS transistor for access.

Claim 6

Dependent Claim 161 words

A static RAM formed on a semiconductor integrated circuit of a master slice type formed by arranging a plurality of basic cells, each of said plurality of basic cells composed of a P-channel type MOS transistor and an N-channel type MOS transistor, on the same semiconductor chip in longitudinal and transversal directions, said static RAM comprising: a first MOS transistor of a memory cell in which a pair of CMOS inverter circuits are connected to each other; a second MOS transistor for access which is connected to each of memory nodes and has a word line signal as a gate input, ions being implanted into a channel of at least one of said first and second MOS transistors to change operating characteristics of the memory cell so that an operating state of the memory cell is set to an initial state when a predetermined voltage is applied to the memory cell from a bit line through the MOS transistor for access.

Claim 7

Dependent Claim 56 words

A static RAM as claimed in claim 4, wherein the ions are implanted into one portion of said channel region in said at least one MOS transistor so as to set a threshold voltage in this ionic implanting portion such that no channel is formed at a normal power potential and narrow an effective channel width.

Claim 8

Dependent Claim 58 words

A static RAM as claimed in claim 4, wherein the ions are implanted into an entire region of said channel in said at least one MOS transistor having the implanted ions such that a threshold voltage of said at least one MOS transistor is equal to a predetermined value for forming the channel at a normal power potential.

Claim 9

Dependent Claim 154 words

A master slice type semiconductor integrated circuit apparatus comprising: a basic cell region in which a plurality of basic cells are arranged, each of the basic cells including a plurality of MOS transistors, each of said plurality of MOS transistors having source and drain section diffusive regions formed on a semiconductor substrate and a gate electrode formed on a channel between said source and drain section diffusive regions through a gate insulating film; wherein ions are implanted into a part of the channel of at least one of the plurality of MOS transistors included in a basic cell to change the effective channel width of said at least one of the plurality of MOS transistors in such a manner that a threshold level of voltage of the implanted part is set at a voltage level in which said part of the channel does not operate within a normal operating voltage of a current source.

Claim 10

Dependent Claim 154 words

A master slice type semiconductor integrated circuit apparatus comprising: a basic cell region in which a plurality of basic cells are arranged, each of the basic cells including a plurality of MOS transistors, each of said plurality of MOS transistors having source and drain section diffusive regions formed on a semiconductor substrate and a gate electrode formed on a channel between said source and drain section diffusive regions through a gate insulating film; wherein ions are implanted into a part of the channel of at least one of the plurality of MOS transistors included in a basic cell to change the effective channel width of said at least one of the plurality of MOS transistors in such a manner that a threshold level of voltage of the implanted part is set at a voltage level in which said part of the channel does not operate within a normal operating voltage of a current source.

Claim 11

Dependent Claim 31 words

A master slice type semiconductor integrated circuit apparatus according to claim 7, wherein the ions are implanted in such a manner as to change a threshold level of a logic element.

Claim 12

Dependent Claim 39 words

A master slice type semiconductor integrated circuit apparatus according to claim 7, wherein the apparatus is constructed in such a manner as to control an ON electric current of said at least one of the plurality of MOS transistors.

Claim 13

Dependent Claim 46 words

A master slice type semiconductor integrated circuit apparatus according to claim 7, wherein the apparatus is constructed in such a manner as to control a rising up or a falling down of an output signal of said at least one of the plurality of MOS transistors.

Claim 14

Dependent Claim 39 words

A master slice type semiconductor integrated circuit apparatus as set forth in claim 7, wherein the apparatus is constructed as a SRAM in which characteristics of memory cells are changed and a writing is executed by a single signal.

Claim 15

Dependent Claim 35 words

A master slice type semiconductor integrated circuit apparatus as set forth in claim 7, wherein the apparatus is constructed as a SRAM in which characteristics of memory cells are changed and an initializing is executed.

Claim 16

Dependent Claim 130 words

A master slice type semiconductor integrated circuit apparatus comprising: a basic cell region in which a plurality of basic cells are arranged, each of the basic cells including a MOS transistor; said MOS transistor having source and drain diffusive regions formed on a semiconductor substrate; wherein ions are implanted into all of the channel of at least one of the MOS transistors in such a manner that a threshold level of voltage of said channel is set at a voltage level in which said channel does not operate within a normal operating voltage of a current source so that a gate electrode of said at least one MOS transistor is used as a wiring formed on said channel between said source and drain diffusive regions through a gate insulating film.

Claim 17

Dependent Claim 130 words

A master slice type semiconductor integrated circuit apparatus comprising: a basic cell region in which a plurality of basic cells are arranged, each of the basic cells including a MOS transistor; said MOS transistor having source and drain diffusive regions formed on a semiconductor substrate; wherein ions are implanted into all of the channel of at least one of the MOS transistors in such a manner that a threshold level of voltage of said channel is set at a voltage level in which said channel does not operate within a normal operating voltage of a current source so that a gate electrode of said at least one MOS transistor is used as a wiring formed on said channel between said source and drain diffusive regions through a gate insulating film.

Claim 18

Dependent Claim 155 words

A master slice type semiconductor integrated circuit apparatus comprising: a basic cell region in which a plurality of basic cells are arranged, each of the basic cells including a plurality of MOS transistors; each of said plurality of MOS transistors having source and drain section diffusive regions implanted with impurities of a conductivity type opposite to that in said diffusive regions formed on a semiconductor substrate and a gate electrode formed on a channel through a gate insulating film; wherein impurities are deeply implanted into the source and drain diffusive regions of a first one of said plurality of MOS transistors at a high density, and a breakdown voltage of a first PN-junction between the diffusive region and the substrate of the first MOS transistor is lower than the breakdown voltage of a second PN-junction between the substrate and the diffusive region of a second MOS transistor into which the impurities are not deeply implanted.

Claim 19

Dependent Claim 155 words

A master slice type semiconductor integrated circuit apparatus comprising: a basic cell region in which a plurality of basic cells are arranged, each of the basic cells including a plurality of MOS transistors; each of said plurality of MOS transistors having source and drain section diffusive regions implanted with impurities of a conductivity type opposite to that in said diffusive regions formed on a semiconductor substrate and a gate electrode formed on a channel through a gate insulating film; wherein impurities are deeply implanted into the source and drain diffusive regions of a first one of said plurality of MOS transistors at a high density, and a breakdown voltage of a first PN-junction between the diffusive region and the substrate of the first MOS transistor is lower than the breakdown voltage of a second PN-junction between the substrate and the diffusive region of a second MOS transistor into which the impurities are not deeply implanted.

Claim 20

Dependent Claim 33 words

A master slice type semiconductor integrated circuit apparatus as claimed in claim 14, wherein said first PN-junction having the lower breakdown voltage is used as a surge protecting element in a terminal section.

Claim 21

Dependent Claim 25 words

A master slice type semiconductor integrated circuit apparatus as claimed in claim 14, wherein said first PN-junction having the lower breakdown voltage has Zener characteristics.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1997-02-07	1997-08-09	1998-02-08	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2001-02-07	2001-08-09	2002-02-08	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2005-02-07	2005-08-09	2006-02-08	$7700.00	Window Closed / Lapsed

Array of field effect transistors of different threshold voltages in same semiconductor integrated circuit

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