Abstract An integrated circuit structure includes a substrate, diffused regions formed in the upper surface of the substrate, and thin and thick insulative regions, polycrystalline regions, and metallic interconnections selectively formed overlying selected areas of the substrate surface. An insulating passivation layer overlying the integrated circuit provides mechanical protection for the integrated circuit. Openings are selectively formed in the passivation layer overlying a portion of the integrated circuit at a position other than that of a bonding pad, and above one of the polycrystalline regions positioned over one of the thin insulating regions. The openings may be used to perform ion implantation to modify theelectrical characteristics, such as the threshold voltage, of the integrated circuit at those locations. The disturbance produced in the lattice structure of the silicon substrate during selective ion implantation may, in one aspect of the invention, not be annealed out in subsequent processing steps such that the remaining lattice disturbance further modifies the threshold voltage at the selected implanted locations.
An M.O.S. integrated circuit comprising a substrate, source, drain, and channel regions of at least first and second M.O.S. transistors being formed in an upper surface of said substrate, a conductive interconnection system formed over said surface of said substrate, said interconnection system including a layer of doped polycrystalline silicon underlying, and being self-aligned with, a metallic layer, an opening selectively formed in said metallic layer, thereby to expose a portion of said layer of doped polycrystalline silicon underlying said opening in said metallic layer, said opening and said exposed portion of said layer of doped polycrystalline silicon directly overlying the channel region of at least one of said first and second transistors at which at least one electrical characteristic is made different from that associated with the other of said first and second transistors by the introduction of impurities into the channel region of said at least one of said first and second transistors through said opening in said metallic layer and the thus exposed portion of said layer of doped polycrystalline silicon.
Claim 2
Dependent Claim
174 words
An M.O.S. integrated circuit comprising a substrate, source, drain, and channel regions of at least first and second M.O.S. transistors being formed in an upper surface of said substrate, a conductive interconnection system formed over said surface of said substrate, said interconnection system including a layer of doped polycrystalline silicon underlying, and being self-aligned with, a metallic layer, an opening selectively formed in said metallic layer, thereby to expose a portion of said layer of doped polycrystalline silicon underlying said opening in said metallic layer, said opening and said exposed portion of said layer of doped polycrystalline silicon directly overlying the channel region of at least one of said first and second transistors at which at least one electrical characteristic is made different from that associated with the other of said first and second transistors by the introduction of impurities into the channel region of said at least one of said first and second transistors through said opening in said metallic layer and the thus exposed portion of said layer of doped polycrystalline silicon.
Claim 3
Dependent Claim
13 words
The integrated circuit of claim 1, in which said metallic layer comprises aluminum.