US5083178A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor cmos gate array
Assignee: Sony Corp
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Filing: 1990-08-24
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Granted: 1992-01-21
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Expires: 2010-08-24
Abstract
Abstract A semiconductor device of a master slice type comprises a basic cell comprising: first and second MOS transistors of a first conductivity type in each of which one of a source region and a drain region is commonly used; third and fourth MOS transistors of the first conductivity type in each of which one of a source region and a drain region is commonly used; fifth and sixth MOS transistors of a second conductivity type in each of which one of a source region and a drain region is commonly used; and seventh and eighth MOS transistors of the second conductivity type in each of which one of a source region and a drain region is commonly used. Gate electrodes of the first and third MOS transistors are commonly used, gate electrodes of the second and fourth MOS transistors are commonly used, and gate electrodes of the fifth and seventh MOS transistors are commonly used.
Inventors
- 👤 Takaji Otsu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 06:34
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/90; H10D84/903; H10D84/907; H10D84/909; H10D84/935; H10D84/937; H10D84/938; Y; Y10; Y10S; Y10S257/00; Y10S257/903
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
145 words
A semiconductor device of a master slice type, comprising a basic cell comprising: first and second MOS transistors of a first conductivity type in each of which one of a source region and a drain region is commonly used; third and fourth MOS transistors of the first conductivity type in each of which one of a source region and a drain region is commonly used; fifth and sixth MOS transistors of a second conductivity type in each of which one of a source region and a drain region is commonly used; and seventh and eighth MOS transistors of the source region and a drain region is commonly used, gate electrodes of said first and third MOS transistors being commonly used, gate electrodes of said second and fourth MOS transistors being commonly used, and gate electrodes of said fifth and seventh MOS transistors being commonly used.
Claim 2
Dependent Claim
145 words
A semiconductor device of a master slice type, comprising a basic cell comprising: first and second MOS transistors of a first conductivity type in each of which one of a source region and a drain region is commonly used; third and fourth MOS transistors of the first conductivity type in each of which one of a source region and a drain region is commonly used; fifth and sixth MOS transistors of a second conductivity type in each of which one of a source region and a drain region is commonly used; and seventh and eighth MOS transistors of the source region and a drain region is commonly used, gate electrodes of said first and third MOS transistors being commonly used, gate electrodes of said second and fourth MOS transistors being commonly used, and gate electrodes of said fifth and seventh MOS transistors being commonly used.
Claim 3
Dependent Claim
22 words
A semiconductor device according to claim 1, wherein gate electrodes of said sixth and eighth MOS transistors are separated from each other.
Claim 4
Dependent Claim
31 words
A semiconductor device according to claims 1 or 2, wherein said first to fourth MOS transistors are p-channel MOS transistors and said fifth to eighth MOS transistors are n-channel MOS transistors.
Claim 5
Dependent Claim
21 words
A semiconductor device according to claims 1 or 2, wherein channel-width-to-channel-length ratios of said fifth to eighth MOS transistors are equal.
Claim 6
Dependent Claim
26 words
A semiconductor device according to claims 1 or 2, wherein a memory cell of a full CMOS static RAM is constructed using one said basic cell.
Claim 7
Dependent Claim
20 words
A semiconductor device according to claims 1 or 2, wherein a NAND circuit is constructed using one said basic cell.
Claim 8
Dependent Claim
20 words
A semiconductor device according to claims 1 or 2, wherein a NOR circuit is constructed using one said basic cell.
References Cited (Backward Citations)
JPS59150446A
Cited
EP0131463A2
Cited
US4783692A
Cited
JPS60177651A
Cited
US4688072A
Cited
US4764798A
Cited
JPS61268040A
Cited
US4982114A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-01-20 | 1995-07-22 | 1996-01-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-01-20 | 1999-07-22 | 2000-01-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-01-20 | 2003-07-22 | 2004-01-21 | $7700.00 | Window Closed / Lapsed |