US4783692A
Expired / Lapsed
US
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CMOS gate array
Assignee: Sharp Corp
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Filing: 1986-04-28
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Granted: 1988-11-08
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Expires: 2006-04-28
Abstract
Abstract A semiconductor device in a CMOS gate array in which a basic cell has inputs by the number of n, wherein the basic cell comprises 2n PMOS transistors and 2r NMOS transistors is disclosed. The basic cell comprises, in a same basic cell, MOS transistors having at least two gate electrodes connected in common and MOS transistors operated on one gate electrode, and a logic circuit is formed by transistors of different gate width.
Inventors
- 👤 Munehiro Uratani
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 00:33
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D30/00; H10D30/60; H10D30/611; H10D84/90; H10D84/903; H10D84/907
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
119 words
A basic cell forming part of a gate array, said gate array having a plurality of cells from which a desired circuit may be constructed, and having only a pair of input lines and a single output line associated with each said cell, the number of transistors in said cell being limited by the number of cell input and output lines, said basic cell comprising: a P-type semiconductor region and an N-type semiconductor region; four gate electrodes extending across each said semiconductor region, said gate electrodes of said cell being commonly connected into gate electrode pairs to form single transistors to thereby increase the effective gate width of each said transistor while better utilizing the area of said cell.
Claim 2
Dependent Claim
119 words
A basic cell forming part of a gate array, said gate array having a plurality of cells from which a desired circuit may be constructed, and having only a pair of input lines and a single output line associated with each said cell, the number of transistors in said cell being limited by the number of cell input and output lines, said basic cell comprising: a P-type semiconductor region and an N-type semiconductor region; four gate electrodes extending across each said semiconductor region, said gate electrodes of said cell being commonly connected into gate electrode pairs to form single transistors to thereby increase the effective gate width of each said transistor while better utilizing the area of said cell.
Claim 3
Dependent Claim
51 words
The basic cell of claim 1 wherein each adjacent pair of electrodes is commonly connected, each common connected adjacent pair of electrodes forming a single transistor input gate, said basic cell comprising two P-type transistors that are formed in said P-region, and two N-type transistors that are formed in said N-region.
Claim 4
Dependent Claim
14 words
The basic cell of claim 1 wherein said cell is of the CMOS type.
Claim 5
Dependent Claim
14 words
The basic cell of claim 2 wherein said gate electrodes are formed of polysilicon.
Claim 6
Dependent Claim
36 words
The basic cell of claim 4 wherein each said transistor diffusion region has a metal wiring connected thereto, the pattern of said metal wiring connecting said transistors and defining the desired circuit within said basic cell.
Claim 7
Dependent Claim
14 words
The basic cell of claim 2 wherein said cell is of the CMOS type.
References Cited (Backward Citations)
US3652906A
Cited
US4412237A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-11-08 | 1992-05-09 | 1992-11-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-11-08 | 1996-05-09 | 1996-11-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-11-08 | 2000-05-09 | 2000-11-08 | $7700.00 | Window Closed / Lapsed |