Patent US5831448A successfully refreshed from Google Patents.
US5831448A
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Function unit for fine-gained FPGA
Assignee: Xilinx Inc
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Filing: 1996-08-27
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Granted: 1998-11-03
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Expires: 2016-08-27
Abstract
Abstract An field programmable gate array (FPGA) of cells arranged in rows and columns is interconnected by a hierarchical routing structure. Switches separate the cells into blocks and into blocks of blocks with routing lines interconnecting the switches to form the hierarchy. Also, select units for allowing memory bits to be addressed both individually and in large and arbitrary groups are disclosed. Further a control store for configuring the FPGA is addressed as an SRAM and can be dynamically reconfigured during operation.
Inventors
- 👤 Thomas A. Kean
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 14:00
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/1733; H03K19/1737; G; G06; G06F; G06F30/00; G06F30/30; G06F30/34; H03K19/177; H03K19/17704; H03K19/17748; H03K19/17752; H03K19/17756; H03K19/17758
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
139 words
A function unit comprising: a plurality of multiplexers; and at least one flip-flop, wherein a first set of said plurality of multiplexers receive input signals from a hierarchical interconnect system, and a second second set of said plurality of multiplexers receive output signals and their complements from said first set of multiplexers, wherein one of said plurality of multiplexers is a function multiplexer which is controlled by an output signal from one of the multiplexers in said second set, wherein said function multiplexer receives output signals from the other multiplexers in said second set, wherein said second set of multiplexers provide input signals to said at least one flip-flop, and wherein one of said plurality of multiplexers receives output signals from said function multiplexer and said at least one flip-flop, and provides an output signal for said function unit.
Claim 2
Dependent Claim
139 words
A function unit comprising: a plurality of multiplexers; and at least one flip-flop, wherein a first set of said plurality of multiplexers receive input signals from a hierarchical interconnect system, and a second second set of said plurality of multiplexers receive output signals and their complements from said first set of multiplexers, wherein one of said plurality of multiplexers is a function multiplexer which is controlled by an output signal from one of the multiplexers in said second set, wherein said function multiplexer receives output signals from the other multiplexers in said second set, wherein said second set of multiplexers provide input signals to said at least one flip-flop, and wherein one of said plurality of multiplexers receives output signals from said function multiplexer and said at least one flip-flop, and provides an output signal for said function unit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-11-02 | 2002-05-04 | 2002-11-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-11-02 | 2006-05-04 | 2006-11-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-11-02 | 2010-05-04 | 2010-11-03 | $7700.00 | Window Closed / Lapsed |