Method and apparatus for programming and verifying programmable elements in programmable devices

Claim 2

Apparatus for programming a programmable integrated circuit having at least one programmable logic array, said at least one programmable logic array having at least m word lines, at least n bit lines, and at least m×n programmable interconnections, said apparatus comprising: means for applying programming data to said array; and means for providing serial address information to said array for indicating, at random, for which of said programmable interconnections said programming data is intended.

Claim 3

Apparatus for programming a programmable integrated circuit having at least one programmable logic array, said at least one programmable logic array having at least m word lines, at least n bit lines, and at least m×n programmable interconnections, said apparatus comprising: means for applying programmable data to said array; and means for providing serial address information to said array for indicating for which of said programmable interconnections said programming data is intended, said serial address information providing means comprising: m shift registers associated with said word lines, n shift registers associated with said bit lines, first address information applying means for applying address information to said m shift registers, second address information applying means for applying address information to said n shift registers, first address information clocking means for applying a clock signal to said m shift registers for shifting said address information applied thereto, second address information clocking means for applying a clock signal to said n shift registers for shifting said address information applied thereto, and means for causing transfer of said programming data to that one of said programmable interconnections indicated by said address information in said m shift registers and said n shift registers.

Claim 4

Apparatus for programming a programmable integrated circuit having at least one programmable logic array, said at least one programmable logic array having at least m word lines, at least n bit lines, and at least m×n programmable interconnections, said apparatus comprising: means for applying programmable data to said array; and means for providing serial address information to said array for indicating for which of said programmable interconnections said programming data is intended, said serial address information providing means comprising: m shift registers associated with said word lines, n shift registers associated with said bit lines, first address information applying means for applying address information to said m shift registers, second address information applying means for applying address information to said n shift registers, first address information clocking means for applying a clock signal to said m shift registers for shifting said address information applied thereto, second address information clocking means for applying a clock signal to said n shift registers for shifting said address information applied thereto, and means for causing transfer of said programming data to that one of said programmable interconnections indicated by said address information in said m shift registers and said n shift registers.

Claim 5

The programming apparatus of claim 2 wherein said programming data transfer causing means comprises means for applying a programming signal to said array after a complete address has been clocked into said shift registers for transferring said programming data to said programmable interconnection.

Claim 6

The programming apparatus of claim 2 further comprising means for verifying said transferred programming data.

Claim 7

The programming apparatus of claim 4 wherein said verifying means comprises means for applying a verification signal for reading back said transferred programming data from said programmable interconnection.

Claim 8

The programming apparatus of claim 2 wherein said programmable logic array is an erasable programmable read-only memory array.

Claim 9

The programming apparatus of claim 6 wherein said erasable programmable read-only memory array is a CMOS erasable programmable read-only memory array.

Claim 10

The programming apparatus of claim 6 wherein said programmable logic array is an electrically erasable programmable read-only memory array.

Claim 11

The programming apparatus of claim 2 wherein said programmable logic array is a fusible link array.

Claim 12

The programming apparatus of claim 2 wherein said programmable logic array is an anti-fuse array.

Claim 13

The programming apparatus of claim 2 wherein said programmable integrated circuit has more than one programmable logic array of possibly varying sizes, one of said programmable logic arrays having at least m word lines and at least n bit lines, said programming apparatus further comprising: a first group select shift register associated with said word lines; means for applying data and clock signals to said first group select shift register for indicating that one of said programmable logic arrays to the word lines of which said address information in said m word line shift registers applies; a second group select shift register associated with said bit lines; and means for applying data and clock signals to said second group select shift register for indicating that one of said programmable logic arrays to the bit lines of which said address information in said n bit line shift registers applies.

Claim 14

The programming apparatus of claim 11 wherein said one of said programmable logic arrays has fewer than m word lines; and an appropriate subset of said m word line shift registers is used for programming said one of said programmable logic arrays.

Claim 15

The programming apparatus of claim 11 wherein: said one of said programmable logic arrays has fewer than n bit lines; and an appropriate subset of said n bit line shift registers is used for programming said one of said programmable logic arrays.

Claim 16

The programming apparatus of claim 11 wherein: said one of said programmable logic arrays has more than m word lines; and said word line group select shift registers indicate for which of said more than m word lines said address information in said m word line shift registers is intended.

Claim 17

The programming apparatus of claim 11 wherein: said one of said programmable logic arrays has more than n bit lines; and said bit line group select shift registers indicate for which of said more than n bit lines said address information in said n bit line shift registers is intended.

Claim 18

The programming apparatus of claim 14 wherein said word line group select shift registers can indicate that said address information in said m word line shift registers is intended for more than m word lines.

Claim 19

The programming apparatus of claim 15 wherein said bit line group select shift registers can indicate that said address information in said n bit line shift registers is intended for more than n word lines.

Claim 20

The programming apparatus of claim 2 wherein said address information in said m shift registers selects one of said word lines for application of programming data on said bit lines.

Claim 21

The programming apparatus of claim 2 wherein said address information in said m shift registers selects more than one of said word lines for application of programming data on said bit lines.

Claim 22

The programming apparatus of claim 2 wherein said address information in said n shift registers selects one of said bit lines for application of programming data on said word lines.

Claim 23

The programming apparatus of claim 2 wherein said address information in said n shift registers selects more than one of said bit lines for application of programming data on said word lines.

Claim 24

The programming apparatus of claim 2 wherein said first and second address information applying means are combined, said first and second address information clocking means controlling application of address information to said m shift registers and said n shift registers.

Claim 25

The programming apparatus of claim 2 wherein said first and second address information clocking means are combined, said first and second address information applying means controlling application of address information to said m shift registers and said n shift registers.