US5047983A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor storage device with redundancy arrangement
Assignee: Sumitomo Chemical Co Ltd
•
Filing: 1990-09-20
•
Granted: 1991-09-10
•
Expires: 2010-09-20
Abstract
Abstract In a semiconductor storage device having a spare memory, an input address signal is checked by an address comparator circuit. When the input address signal indicates an address which is to be relieved, the spare memory is selected instead of a memory array on the basis of the output of the address comparator circuit at that time. In conventional system, the access time of the semiconductor memory is restricted substantially by the operating time of the address comparator circuit during this operation. Accordingly, for enabling a quick access of the semiconductor memory, an address signal to be supplied to the address comparator circuit is output from a proceeding stage circuit of a plurality of amplification stages which form an address buffer circuit.
Inventors
- 👤 Hidetoshi Iwai
- 👤 Kazuyuki Miyazawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 15:55
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C29/00; G11C29/70; G11C29/78; G11C29/84; G11C29/842
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
200 words
A semiconductor storage device comprises: a memory array; a first circuit receiving an input address signal; a second circuit made to respond to an output signal of said first circuit and forming an address signal to be supplied to an address decoder; said address decoder being coupled to said memory array, and decoding said address signal formed by said second circuit so as to form a selection signal to be supplied to said memory array; a spare memory; an address comparator circuit receiving an output signal of said first circuit, wherein said address comparator circuit includes store means for storing a defective address signal and means for comparing the defective address signal stored in said storage means with the output signal of said first circuit; and a selection signal forming circuit made to respond to an output signal of said address comparator circuit and forming a selection signal for said spare memory, wherein said first circuit is formed of an address buffer circuit, and further wherein said second circuit is formed of a pre-decoder decoding the address signal supplied from said address buffer circuit, and forming, based on this signal, a decoded signal to be supplied to said address decoder.
Claim 2
Dependent Claim
200 words
A semiconductor storage device comprises: a memory array; a first circuit receiving an input address signal; a second circuit made to respond to an output signal of said first circuit and forming an address signal to be supplied to an address decoder; said address decoder being coupled to said memory array, and decoding said address signal formed by said second circuit so as to form a selection signal to be supplied to said memory array; a spare memory; an address comparator circuit receiving an output signal of said first circuit, wherein said address comparator circuit includes store means for storing a defective address signal and means for comparing the defective address signal stored in said storage means with the output signal of said first circuit; and a selection signal forming circuit made to respond to an output signal of said address comparator circuit and forming a selection signal for said spare memory, wherein said first circuit is formed of an address buffer circuit, and further wherein said second circuit is formed of a pre-decoder decoding the address signal supplied from said address buffer circuit, and forming, based on this signal, a decoded signal to be supplied to said address decoder.
Claim 3
Dependent Claim
104 words
A semiconductor storage device according to claim 1 wherein further comprises: a word line driver receiving the selection signal output from said address decoder, and forming, based on this signal, a selection signal to be supplied to a word line in said memory array, said spare memory having a word line selected by the selection signal delivered from said selection signal forming circuit, and said selection signal forming circuit delivering a signal for stopping the operation of said word line driver and a signal for driving the work line in said spare memory, in response to the output signal of said address comparator circuit.
Claim 4
Dependent Claim
24 words
A semiconductor storage device according to claim 2, wherein each of said first and second circuits is formed of a plurality of inverter circuits.
Claim 5
Dependent Claim
60 words
A semiconductor storage device according to claim 3, wherein the inverter circuits forming said first and second circuits are formed of insulated gate field-effect transistors, and further wherein the insulated gate field-effect transistors for forming the output signal of said second circuit are made larger than the insulated gate field-effect transistors for forming the output signal of said first circuit.
Claim 6
Dependent Claim
21 words
A semiconductor storage device according to claim 4, wherein each of said inverter circuits is formed of a CMOS inverter circuit.
Claim 7
Dependent Claim
235 words
A semiconductor storage device comprising: a memory array including a plurality of memory cells; a first circuit receiving an input address signal; a second circuit coupled to said first circuit and forming an address signal in response to an output signal of said first circuit; an address decoder coupled to said second circuit and forming a selection signal by decoding the address signal of said second circuit; a word line driver coupled to said address decoder and to said memory array, and forming a selection signal to be supplied to a word line in said memory array; a spare memory including a plurality of memory cells; an address comparator circuit coupled to said first circuit and receiving an output signal of said first circuit and receiving an output signal of said first circuit, wherein said address comparator circuit includes store means for storing a defective address signal and comparator means for comparing the defective address signal stored in said store means with the output signal of said first circuit; and a selection signal forming circuit responsive to an output signal of said comparator means for forming a selection signal for said spare memory, wherein said first circuit includes an address buffer circuit, and wherein said second circuit includes a pre-decoder for decoding an address signal supplied from said address buffer circuit, so as to form the address signal to be supplied to said address decoder.
Claim 8
Dependent Claim
235 words
A semiconductor storage device comprising: a memory array including a plurality of memory cells; a first circuit receiving an input address signal; a second circuit coupled to said first circuit and forming an address signal in response to an output signal of said first circuit; an address decoder coupled to said second circuit and forming a selection signal by decoding the address signal of said second circuit; a word line driver coupled to said address decoder and to said memory array, and forming a selection signal to be supplied to a word line in said memory array; a spare memory including a plurality of memory cells; an address comparator circuit coupled to said first circuit and receiving an output signal of said first circuit and receiving an output signal of said first circuit, wherein said address comparator circuit includes store means for storing a defective address signal and comparator means for comparing the defective address signal stored in said store means with the output signal of said first circuit; and a selection signal forming circuit responsive to an output signal of said comparator means for forming a selection signal for said spare memory, wherein said first circuit includes an address buffer circuit, and wherein said second circuit includes a pre-decoder for decoding an address signal supplied from said address buffer circuit, so as to form the address signal to be supplied to said address decoder.
Claim 9
Dependent Claim
74 words
A semiconductor storage device according to claim 6, wherein said spare memory includes a word line coupled to memory cells and supplied with the selection signal delivered from said selection signal forming circuit, and wherein said selection signal forming circuit delivers a signal for stopping the operation of said word line driver and a signal for driving the word line in said spare memory, in response to the output signal of said comparator means.
Claim 10
Dependent Claim
24 words
A semiconductor storage device according to claim 7, wherein each of said first and second circuits is formed of a plurality of inverter circuits.
Claim 11
Dependent Claim
59 words
A semiconductor storage device according to claim 8, wherein the inverter circuits forming said first and second circuits are formed of insulated gate field-effect transistors, and wherein the insulated gate field-effect transistors for forming the output signal of said second circuit are made larger than the insulated gate field-effect transistors for forming the output signal of said first circuit.
Claim 12
Dependent Claim
21 words
A semiconductor storage device according to claim 9, wherein each of said inverter circuits is formed of a CMOS inverter circuit.
Claim 13
Dependent Claim
23 words
A semiconductor storage device according to claim 7, wherein each of said memory cells includes a storage capacitor and an address selecting MOSFET.
Claim 14
Dependent Claim
19 words
A semiconductor storage device according to claim 4, wherein said address buffer circuit is formed of a CMOS circuit.
Claim 15
Dependent Claim
15 words
A semiconductor storage device according to claim 12, wherein said CMOS circuit includes CMOS inverters.
References Cited (Backward Citations)
GB1260914A
Cited
GB1311997A
Cited
DE2237671A1
Cited
GB1398438A
Cited
US4104735A
Cited
US4247921A
Cited
EP0029322A1
Cited
DE3138363A1
Cited
JPS57198593A
Cited
US4532607A
Cited
US4538245A
Cited
EP0095721A2
Cited
GB2129585A
Cited
EP0124900A2
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-09-09 | 1995-03-11 | 1995-09-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-09-09 | 1999-03-11 | 1999-09-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-09-09 | 2003-03-11 | 2003-09-10 | $7700.00 | Window Closed / Lapsed |