Reduntant type memory circuit with an improved clock generator

Claim 2

In a memory circuit of the type having a normal array of memory cells, a redundant array of memory cells, access means for receiving address information applied to said memory circuit and for accessing cells in said normal array in accordance with said address information when enabled, an address control circuit responsive to said address information for accessing, when enabled, at least one cell of said redundant array in accordance with said address information when said address information corresponds to the address of a faulty cell in said normal array, means for providing a control signal, a first control circuit responsive to said control signal for enabling said address control circuit, and a second control. circuit responsive to said control signal for enabling said access circuit, wherein said second control circuit comprises programmable means for varying the length of a time period between activation of said control signal and the enabling of said access means.

Claim 3

The memory circuit according to Claim 1, wherein said programmable means has first and second states and varies said time period between first and second values corresponding to said first and second states, respectively.

Claim 4

The memory circuit according to Claim 2, wherein said programmable means has said first state when said first cell is a faulty memory cell, and has said second state when said normal array includes no faulty memory cell, and wherein said second value is smaller than said first value.

Claim 5

The memory circuit according to Claim 2, wherein said first value is longer than a time period from said activation of said control signal to generation of said second signal.

Claim 6

The memory circuit according to Claim 3, wherein said first value is longer than a time period from said activation of said control signal to generation of said second signal.

Claim 7

The memory circuit according to Claim 1, wherein said address control circuit includes a programmable type redundant decoder for accessing said redundant array and an inhibit control circuit for inhibiting the operation of said access means when said redundant decoder selects said redundant array.

Claim 8

The memory circuit according to Claim 4, wherein said redundant decoder includes a plurality of programmable elements.

Claim 9

The memory circuit according to Claim 7, wherein each of said programmable elements includes a fusible link made of polycrystalline silicon.

Claim 10

The memory circuit according to Claim 1, wherein said programmable means includes a fusible link made of polycrystalline silicon.

Claim 11

A memory circuit comprising a first array of memory cells arrayed in rows and columns, a second array of memory cells arrayed in rows and columns, a row address buffer receiving a plurality of row address signals for operatively generating their true and complementary signals, a first row decoder responsive to said true and complementary signals for operatively selecting one of the rows of said first array a second row decoder responsive to said true and complementary signals for operatively selecting one of the rows of said second array, a control circuit coupled to said first row decoder and operatively inhibiting the operation of said second row decoder when said first row decoder selects said first array, a first timing circuit responsive to a control signal for generating a first timing signal for enabling said address buffer, a second timing circuit responsive to said first timing signal for generating a second timing signal for enabling said first row decoder, a third timing circuit responsive to said second timing signal for generating a third timing signal for enabling said control circuit, a multi-input timing circuit having a first input terminal adapted to receive said third timing signal and a second input terminal, each of said timing signals having active and inactive potential levels, said multi-input timing circuit generating a fourth timing signal for enabling said second row decoder when a potential of any one of said first and second input terminals is set at an active level, and a programmable connection circuit for connecting said second input terminal of said multi-input timing circuit to the output of said first timing circuit.

Claim 12

A memory circuit comprising a first array of memory cells arrayed in rows and columns, a second array of memory cells arrayed in rows and columns, a row address buffer receiving a plurality of row address signals for operatively generating their true and complementary signals, a first row decoder responsive to said true and complementary signals for operatively selecting one of the rows of said first array a second row decoder responsive to said true and complementary signals for operatively selecting one of the rows of said second array, a control circuit coupled to said first row decoder and operatively inhibiting the operation of said second row decoder when said first row decoder selects said first array, a first timing circuit responsive to a control signal for generating a first timing signal for enabling said address buffer, a second timing circuit responsive to said first timing signal for generating a second timing signal for enabling said first row decoder, a third timing circuit responsive to said second timing signal for generating a third timing signal for enabling said control circuit, a multi-input timing circuit having a first input terminal adapted to receive said third timing signal and a second input terminal, each of said timing signals having active and inactive potential levels, said multi-input timing circuit generating a fourth timing signal for enabling said second row decoder when a potential of any one of said first and second input terminals is set at an active level, and a programmable connection circuit for connecting said second input terminal of said multi-input timing circuit to the output of said first timing circuit.

Claim 13

The memory circuit according to Claim 10, wherein said programmable connection circuit includes a fusible link inserted in the electrical path between said second input terminal and the output of said first timing circuit.

Claim 14

The memory circuit according to Claim 11, wherein said fusible link is made of polycrystalline silicon.

Claim 15

The memory circuit according to Claim 10, wherein said programmable connection circuit includes a first transistor inserted in the electrical path between said second input terminal and the output of said first timing circuit, a series circuit of a second transistor and a programmable resistor element connected at an intermediate junction, said first transistor having a control electrode for controlling the conductivity thereof, and connection means for connecting said control electrode to said intermediate junction.

Claim 16

The memory circuit according to Claim 13, wherein said programmable resistor element is made of polycrystalline silicon.

Claim 17

The memory circuit according to Claim 1, wherein said second control circuit comprises first means for providing an enabling signal to said access circuit is response to either one of two inputs, second means for generating a first signal delayed with respect to said control signal and for providing said first signal to one of said two inputs of said first means and third means for selectively providing said control signal to the other of said two inputs to said first means.

Claim 18

The memory circuit according to Claim 15, wherein said third means comprises said programmable means and provides said control signal to said other input only in said second state when said normal array includes no faulty memory cell.

Claim 19

The memory circuit according to Claim 1, wherein said second control circuit comprises an OR circuit for enabling said access circuit in response to either of two inputs, first delay means for providing said control signal to one of said two inputs with a predetermined delay, and programmable second delay means for providing said control signal to the other of said two inputs with a second predetermined delay less than said first delay in said first state.

Claim 20

The memory circuit according to Claim 17, wherein said programmable means has said first state when said first cell is a faulty memory cell and has said second state when said normal array includes no faulty memory cell, and wherein said second value is smaller than said first value.

Claim 21

A memory circuit, comprising: a normal memory cell array; a first decoder circuit for accessing a cell in said normal cell array, when enabled, in accordance with address information applied to said memory circuit; a redundant memory cell array; a second decoder circuit for accessing a cell in said redundant memory cell array,when enabled, in accordance with said address information; and a programmable control circuit for enabling said first decoder at a first timing when said normal cell array includes no faulty cells and for enabling said first decoder at a second timing later than said first timing when said normal array includes at least one faulty memory cell.

Claim 22

A memory circuit, comprising: a normal memory cell array; a first decoder circuit for accessing a cell in said normal cell array, when enabled, in accordance with address information applied to said memory circuit; a redundant memory cell array; a second decoder circuit for accessing a cell in said redundant memory cell array,when enabled, in accordance with said address information; and a programmable control circuit for enabling said first decoder at a first timing when said normal cell array includes no faulty cells and for enabling said first decoder at a second timing later than said first timing when said normal array includes at least one faulty memory cell.

Claim 23

The memory circuit according to Claim 19, wherein said programmable timing circuit enables said second decoder prior to said first decoder when said normal array includes at least one faulty cell.