DE3138363A1
Expired / Lapsed
DE
⏱️ 0.0 years remaining
REDUNDANCY CIRCUIT FOR STORAGE
Assignee: Intel Corp
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Filing: 1981-09-26
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Granted: —
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Expires: 2001-09-26
Abstract
Abstract An improved addressing means for single chip memories which include a plurality of redundant lines and associated cells is described. Y address signals are used during programming to select and program redundant X decoders. The redundancy apparatus is implemented without any additional package pins and programming may be performed after packaging. The apparatus includes means for permanently disabling all further programming of the redundancy circuitry to prevent inadvertent programming by a user.
Inventors
- 👤 Alan C. 95051 Santa Clara Folmsbee
- 👤 Kim 95008 Campbell Calif. Kokkonen
- 👤 William J. 94038 Moss Beach Calif. Spaw
Bibliographic Details
Application Number
—
Jurisdiction
DE
Data Source
google_patents
Last Synchronized
2026-11-03 21:39
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G11C29/785; G11C29/83; G11C29/832
Claims Analysis
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References Cited (Backward Citations)
US4047163A
Cited
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