Memory system for reliably writing addresses with reduced power consumption

Claim 2

A memory system for reliably writing address inputs thereto for subsequent logical to physical address translation, comprising: a content addressable memory (CAM) having a plurality of entry locations, each entry location storing a predetermined number of address bits and a validity bit indicating the validity of the address bits of a predetermined entry location, each entry location of the CAM having a match output for indicating presence of matching validated address bits between an entry location and a received input logical address, each entry of the CAM also having a write select input indicating selection of an entry location to be written to; driver means coupled to the output of each entry of the CAM, the driver means having a control input coupled to the write select input for transitioning the match output from a first logic state to a second logic state in response to the write select input and logical address inputs; feedback means coupling the match output of each entry location of the CAM to the validity bit of each entry for setting the validity bit of a selected entry to a valid state only after a successful write of the selected entry of the CAM; and a second memory coupled to the CAM having a plurality of entry locations, each of which corresponds to a predetermined entry location of the CAM, each entry location of the second memory having an input coupled to a predetermined match output of the CAM, the second memory providing a physical address in response to the received input logical address.

Claim 3

The memory system of claim 1 wherein the driver means further comprise a single transistor per entry of the CAM, each transistor having a first current electrode coupled to a power supply voltage terminal, a control electrode coupled to the write select input, and a second current electrode coupled to the match output.

Claim 4

The memory system of claim 2 wherein the second memory is a random access memory (RAM), each entry location of the RAM being coupled to a second current electrode of a predetermined single transistor of the driver means and to a predetermined match output of the CAM.

Claim 5

In a memory system for translating logical addresses to physical addresses having a content addressable memory (CAM) array and a random access memory (RAM) array, a method of writing address inputs to both the CAM array and the RAM array, comprising the steps of: implementing the CAM array with a plurality of entry locations, the CAM array having an input for receiving an input logical address; storing a predetermined number of address bits and a validity bit in each entry location of the CAM array, the validity bit indicating the validity of the address bits of a predetermined entry location, each entry location of the CAM array having a match output for indicating presence of matching validated address bits between an entry location and the received input logical address, each entry of the CAM array also having a write select input indicating selection of an entry location to be written to; coupling one of a plurality of driver transistors to the output of each entry of the CAM array, each driver transistor having a control electrode coupled to the write select input for transitioning the match output from a first logic state to a second logic state in response to the write select input and the received input logical address; in each entry location of the CAM array, coupling the match output thereof to the validity bit thereof for setting the validity bit of a selected entry to a valid state only after a successful write of the selected entry of the CAM array; coupling the RAM array to the CAM array, the RAM array having a plurality of entry locations, each of which corresponds to a predetermined entry location of the CAM array, each entry location of the RAM array having an input coupled to a predetermined match output of the CAM array; and providing a physical address at an output of the RAM array in response to the input logical address.

Claim 6

In a memory system for translating logical addresses to physical addresses having a content addressable memory (CAM) array and a random access memory (RAM) array, a method of writing address inputs to both the CAM array and the RAM array, comprising the steps of: implementing the CAM array with a plurality of entry locations, the CAM array having an input for receiving an input logical address; storing a predetermined number of address bits and a validity bit in each entry location of the CAM array, the validity bit indicating the validity of the address bits of a predetermined entry location, each entry location of the CAM array having a match output for indicating presence of matching validated address bits between an entry location and the received input logical address, each entry of the CAM array also having a write select input indicating selection of an entry location to be written to; coupling one of a plurality of driver transistors to the output of each entry of the CAM array, each driver transistor having a control electrode coupled to the write select input for transitioning the match output from a first logic state to a second logic state in response to the write select input and the received input logical address; in each entry location of the CAM array, coupling the match output thereof to the validity bit thereof for setting the validity bit of a selected entry to a valid state only after a successful write of the selected entry of the CAM array; coupling the RAM array to the CAM array, the RAM array having a plurality of entry locations, each of which corresponds to a predetermined entry location of the CAM array, each entry location of the RAM array having an input coupled to a predetermined match output of the CAM array; and providing a physical address at an output of the RAM array in response to the input logical address.

Claim 7

The method of claim 4 wherein the step of coupling one driver transistor to the output of each entry of the CAM array further comprises coupling a first current electrode of each driver transistor to a power supply voltage terminal, coupling a control electrode of each driver transistor to a predetermined write select output of each entry location, the write select output of each entry location indicating successful completion of a write operation to the entry location, and coupling a second current electrode to a predetermined match output.

Claim 8

An address translation memory system than guarantees loading of a first address in an entry of a first storage device prior to loading a second address in a corresponding entry of a second storage device, comprising: a plurality of address drivers having an input for receiving a logical address and providing a plurality of corresponding true and complement address bits; a content addressable memory (CAM) coupled to the plurality of address drivers and having a plurality of entry locations, each entry location having a plurality of cell circuits which each receive predetermined true and complement address bits for selective storage or comparison with previously stored address bits, each entry location having a validity bit for indicating a valid state of the entry location after a successful write to the respective entry location and having a match output for indicating presence of matching validated data between an entry location and an input address; driver means coupled to the match output of each entry location of the CAM, said driver means transitioning the match output of a predetermined match output of a predetermined entry location of the CAM from a first logic state to a second logic state in response to the validity bit; feedback means coupling the match output of each entry location of the CAM to the validity bit of each entry for setting the validity bit of a selected entry to a valid state only after a successful write of the selected entry of the CAM; and a random access memory (RAM) coupled to the CAM and having a plurality of entry locations, each of which corresponds to a predetermined entry location of the CAM, each entry location of the RAM having an input coupled to a predetermined match output of the CAM, the RAM providing a physical address in response to the received input logical address.

Claim 9

An address translation memory system than guarantees loading of a first address in an entry of a first storage device prior to loading a second address in a corresponding entry of a second storage device, comprising: a plurality of address drivers having an input for receiving a logical address and providing a plurality of corresponding true and complement address bits; a content addressable memory (CAM) coupled to the plurality of address drivers and having a plurality of entry locations, each entry location having a plurality of cell circuits which each receive predetermined true and complement address bits for selective storage or comparison with previously stored address bits, each entry location having a validity bit for indicating a valid state of the entry location after a successful write to the respective entry location and having a match output for indicating presence of matching validated data between an entry location and an input address; driver means coupled to the match output of each entry location of the CAM, said driver means transitioning the match output of a predetermined match output of a predetermined entry location of the CAM from a first logic state to a second logic state in response to the validity bit; feedback means coupling the match output of each entry location of the CAM to the validity bit of each entry for setting the validity bit of a selected entry to a valid state only after a successful write of the selected entry of the CAM; and a random access memory (RAM) coupled to the CAM and having a plurality of entry locations, each of which corresponds to a predetermined entry location of the CAM, each entry location of the RAM having an input coupled to a predetermined match output of the CAM, the RAM providing a physical address in response to the received input logical address.

Claim 10

The address translation memory system of claim 6 wherein the driver means further comprise a plurality of transistors, the transistors comprising a transistor being connected between a power supply voltage terminal and each match output of the CAM.

Claim 11

The address translation memory system of claim 7 wherein each transistor of the plurality of transistors is an MOS transistor.