Field programmable gate array with mask programmed analog function circuits

Claim 2

A mixed signal integrated circuit architecture comprising: a mask programmable portion comprising: a plurality of mask programmed analog function circuits, each of said analog function circuits having at least one input and at least one output; and a first group of input/output pads, at least one of said input/output pads of said first group connected to an input of one of said analog function circuits; and a field programmable gate array portion comprising: a plurality of programmable digital logic function modules, each of said digital logic function modules having a plurality of inputs and at least one output; a second group of input/output pads; a plurality of interconnect conductors, each of said interconnect conductors divided into one or more segments, at least some first ones of said segments running in a first direction and at least some second ones of said segments running in a second direction different from said first direction to form intersections between said first ones and said second ones of said segments, said interconnect conductors forming intersections with said plurality of inputs and said at least one output of said digital logic function modules, said interconnect conductors forming intersections with said second group of input/output pads, said interconnect conductors forming intersections with said at least one output of one of said analog function circuits from said mask programmable analog portion; and a plurality of user programmable interconnect elements, first ones of said interconnect elements connected between adjoining ones of said segments in a same one of said interconnect conductors, second ones of said interconnect elements connected between intersections of selected ones said first and second segments, third ones of said interconnect elements connected between inputs and outputs of said digital logic function modules and selected interconnect conductors, fourth ones of said interconnect elements connected between intersections of said second group of input/output pads and selected ones of said interconnect conductors, fifth ones of said interconnect elements connected between intersections with said at least one output of one of said analog function circuits and selected ones of said interconnect conductors.

Claim 3

A mixed signal integrated circuit architecture comprising: a mask programmable portion comprising: a plurality of mask programmed analog function circuits, each of said analog function circuits having at least one input and at least one output; and a first group of input/output pads, at least one of said input/output pads of said first group connected to an output of one of said analog function circuits; and a field programmable gate array portion comprising: a plurality of programmable digital logic function modules, each of said digital logic function modules having a plurality of inputs and at least one output; a second group of input/output pads; a plurality of interconnect conductors, each of said interconnect conductors divided into one or more segments, at least some first ones of said segments running in a first direction and at least some second ones of said segments running in a second direction different from said first direction to form intersections between said first ones and said second ones of said segments, said interconnect conductors forming intersections with said plurality of inputs and said at least one output of said digital logic function modules, said interconnect conductors forming intersections with said second group of input/output pads, said interconnect conductors forming intersections with said at least one input of one of said analog function circuits from said mask programmable analog portion; and a plurality of user programmable interconnect elements, first ones of said interconnect elements connected between adjoining ones of said segments in a same one of said interconnect conductors, second ones of said interconnect elements connected between intersections of selected ones said first and second segments, third ones of said interconnect elements connected between inputs and outputs of said digital logic function modules and selected interconnect conductors, fourth ones of said interconnect elements connected between intersections of said second group of input/output pads and selected ones of said interconnect conductors, fifth ones of said interconnect elements connected between intersections with said at least one input of one of said analog function circuits and selected ones of said interconnect conductors.

Claim 4

A mixed signal integrated circuit architecture comprising: a mask programmable portion comprising: a plurality of mask programmed analog function circuits, each of said analog function circuits having at least one input and at least one output; and a first group of input/output pads, at least one of said input/output pads of said first group connected to an output of one of said analog function circuits; and a field programmable gate array portion comprising: a plurality of programmable digital logic function modules, each of said digital logic function modules having a plurality of inputs and at least one output; a second group of input/output pads; a plurality of interconnect conductors, each of said interconnect conductors divided into one or more segments, at least some first ones of said segments running in a first direction and at least some second ones of said segments running in a second direction different from said first direction to form intersections between said first ones and said second ones of said segments, said interconnect conductors forming intersections with said plurality of inputs and said at least one output of said digital logic function modules, said interconnect conductors forming intersections with said second group of input/output pads, said interconnect conductors forming intersections with said at least one input of one of said analog function circuits from said mask programmable analog portion; and a plurality of user programmable interconnect elements, first ones of said interconnect elements connected between adjoining ones of said segments in a same one of said interconnect conductors, second ones of said interconnect elements connected between intersections of selected ones said first and second segments, third ones of said interconnect elements connected between inputs and outputs of said digital logic function modules and selected interconnect conductors, fourth ones of said interconnect elements connected between intersections of said second group of input/output pads and selected ones of said interconnect conductors, fifth ones of said interconnect elements connected between intersections with said at least one input of one of said analog function circuits and selected ones of said interconnect conductors.

Claim 5

A mixed signal integrated circuit architecture comprising: a mask programmable portion comprising: a plurality of mask programmed analog function circuits, each of said analog function circuits having at least one input and at least one output; and a first group of input/output pads, at least one of said input/output pads of said first group connected to an input of one of said analog function circuits, at least one of said input/output pads of said first group connected to an output of one of said analog function circuits; and a field programmable gate array portion comprising: a plurality of programmable digital logic function modules, each of said digital logic function modules having a plurality of inputs and at least one output; a second group of input/output pads; a plurality of interconnect conductors, each of said interconnect conductors divided into one or more segments, at least some first ones of said segments running in a first direction and at least some second ones of said segments running in a second direction different from said first direction to form intersections between said first ones and said second ones of said segments, said interconnect conductors forming intersections with said plurality of inputs and said at least one output of said digital logic function modules, said interconnect conductors forming intersections with said second group of input/output pads, said interconnect conductors forming intersections with said at least one output of one of said analog function circuits from said mask programmable analog portion, said interconnect conductors forming intersections with said at least one input of one of said analog function circuits from said mask programmable analog portion; and a plurality of user programmable interconnect elements, first ones of said interconnect elements connected between adjoining ones of said segments in a same one of said interconnect conductors, second ones of said interconnect elements connected between intersections of selected ones said first and second segments, third ones of said interconnect elements connected between inputs and outputs of said digital logic function modules and selected interconnect conductors, fourth ones of said interconnect elements connected between intersections of said second group of input/output pads and selected ones of said interconnect conductors, fifth ones of said interconnect elements connected between intersections with said at least one output of one of said analog function circuits and selected ones of said interconnect conductors, sixth ones of said interconnect elements connected between intersections with said at least one input of one of said analog function circuits and selected ones of said interconnect conductors.

Claim 6

A mixed signal integrated circuit architecture comprising: a mask programmable portion comprising: a plurality of mask programmed analog function circuits, each of said analog function circuits having at least one input and at least one output; and a first group of input/output pads, at least one of said input/output pads of said first group connected to an input of one of said analog function circuits, at least one of said input/output pads of said first group connected to an output of one of said analog function circuits; and a field programmable gate array portion comprising: a plurality of programmable digital logic function modules, each of said digital logic function modules having a plurality of inputs and at least one output; a second group of input/output pads; a plurality of interconnect conductors, each of said interconnect conductors divided into one or more segments, at least some first ones of said segments running in a first direction and at least some second ones of said segments running in a second direction different from said first direction to form intersections between said first ones and said second ones of said segments, said interconnect conductors forming intersections with said plurality of inputs and said at least one output of said digital logic function modules, said interconnect conductors forming intersections with said second group of input/output pads, said interconnect conductors forming intersections with said at least one output of one of said analog function circuits from said mask programmable analog portion, said interconnect conductors forming intersections with said at least one input of one of said analog function circuits from said mask programmable analog portion; and a plurality of user programmable interconnect elements, first ones of said interconnect elements connected between adjoining ones of said segments in a same one of said interconnect conductors, second ones of said interconnect elements connected between intersections of selected ones said first and second segments, third ones of said interconnect elements connected between inputs and outputs of said digital logic function modules and selected interconnect conductors, fourth ones of said interconnect elements connected between intersections of said second group of input/output pads and selected ones of said interconnect conductors, fifth ones of said interconnect elements connected between intersections with said at least one output of one of said analog function circuits and selected ones of said interconnect conductors, sixth ones of said interconnect elements connected between intersections with said at least one input of one of said analog function circuits and selected ones of said interconnect conductors.