US5329181A
Expired / Lapsed
US
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Complementary macrocell feedback circuit
Assignee: NEC Corp
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Filing: 1993-03-05
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Granted: 1994-07-12
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Expires: 2013-03-05
Abstract
Abstract In a programmable logic device having I/O blocks and logic blocks, two lines leading from a region including a logic block and an I/O block alternately provide a logic block output signal and its complement or a logic block output signal and an I/O block input signal. A multiplexer selects between providing on a line leading from an I/O block to an interconnect structure a first signal which is provided by the I/O block when the I/O block is an input buffer and a second signal which is the inverse of a logic signal provided to the I/O block when the I/O block is not an input buffer. Thus in one case two lines which extend from the I/O block to the interconnect structure may carry a) a logic block output signal and b) an I/O block output signal; and in the other case carry a) a logic block output signal and b) the inverse of the logic block output signal.
Inventors
- 👤 David J. Ridgeway
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 14:38
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17736; H03K19/17744; H03K19/17704
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
86 words
A feedback circuit comprising: a first line (14) for providing a logic block output signal; a second line (16) for providing a second signal; means (24) for generating the complement of said logic block output signal; a third line (23); and means (22) for providing on said third line a selected one of said complement of said logic block output signal and said second signal; an interconnect structure (11); and means (19) for programmably connecting said first line and said third line to said interconnect structure.
Claim 2
Dependent Claim
86 words
A feedback circuit comprising: a first line (14) for providing a logic block output signal; a second line (16) for providing a second signal; means (24) for generating the complement of said logic block output signal; a third line (23); and means (22) for providing on said third line a selected one of said complement of said logic block output signal and said second signal; an interconnect structure (11); and means (19) for programmably connecting said first line and said third line to said interconnect structure.
Claim 3
Dependent Claim
63 words
A feedback circuit as in claim 1 in which said means for programmably connecting said first line and said third line to said interconnect structure comprise for each connection a transistor (19) having at gate controlled by said first or third line (14), a source for providing a supply voltage (ground), and a drain connected to another line (12c) in said interconnect structure.
Claim 4
Dependent Claim
83 words
A feedback circuit comprising: a first line (14) for providing a logic block output signal; a second line (16) for providing a second signal; means (24) for generating the complement of said logic block output signal; a third line (23); and means (22) for providing on said third line a selected one of said complement of said logic block output signal and said second signal; in which said means for generating the complement of said logic block output signal comprises an inverter (24).
Claim 5
Dependent Claim
83 words
A feedback circuit comprising: a first line (14) for providing a logic block output signal; a second line (16) for providing a second signal; means (24) for generating the complement of said logic block output signal; a third line (23); and means (22) for providing on said third line a selected one of said complement of said logic block output signal and said second signal; in which said means for generating the complement of said logic block output signal comprises an inverter (24).
Claim 6
Dependent Claim
147 words
A feedback circuit comprising: a logic block (13) for generating a logic block output signal (14); an I/O block (15) for alternatively providing on an external line (17) said logic block output signal and providing on an internal line (16) a signal received from said external line; a first line (23) for providing a first signal; a second line (27) for providing a second signal; and means for providing on said first and second lines a selected one of each of the following pairs of signals: 1) an I/O block output signal and the complement of the I/O block output signal; 2) a logic block output signal and the complement of the logic block output signal; 3) a logic block output signal and an I/O block output signal; and 4) the complement of the I/O block output signal and the complement of the logic block output signal.
Claim 7
Dependent Claim
147 words
A feedback circuit comprising: a logic block (13) for generating a logic block output signal (14); an I/O block (15) for alternatively providing on an external line (17) said logic block output signal and providing on an internal line (16) a signal received from said external line; a first line (23) for providing a first signal; a second line (27) for providing a second signal; and means for providing on said first and second lines a selected one of each of the following pairs of signals: 1) an I/O block output signal and the complement of the I/O block output signal; 2) a logic block output signal and the complement of the logic block output signal; 3) a logic block output signal and an I/O block output signal; and 4) the complement of the I/O block output signal and the complement of the logic block output signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-07-11 | 1998-01-10 | 1998-07-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-07-11 | 2002-01-10 | 2002-07-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-07-11 | 2006-01-10 | 2006-07-12 | $7700.00 | Window Closed / Lapsed |