EP0759662A2
Expired / Lapsed
EP
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Time multiplexed programmable logic device
Assignee: Xilinx Inc
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Filing: 1996-08-16
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Granted: —
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Expires: 2016-08-16
Abstract
Abstract A programmable logic device (PLD) comprises a plurality of configurable logic blocks (CLBs), an interconnect structure for interconnecting the CLBs, and a plurality of programmable logic elements for configuring the CLBs and the interconnect structure. Each CLB includes a combinational element and a sequential logic element, wherein at least one programmable logic element includes a plurality of memory cells for configuring the combinational element and at least one programmable logic element includes a plurality of memory cells for configuring the sequential logic element. A micro register, which stores a plurality of intermediate states of one CLB or interconnect structure, is located at the output of a CLB, the input of a CLB, or elsewhere in the interconnect structure. The PLD includes means for disabling access to at least one of said plurality of memory elements. In one embodiments, the memory cells are RAM cells, whereas in other embodiments the memory cells are ROM cells, or a combination thereof. The PLD switches between configurations sequentially, by random access, or on command from an external or internal signal. This reconfiguration allows the PLD to function in one of N configurations, wherein N is equal to the maximum number of memory cells assigned to each programmable point. In this manner, a PLD with a number M of actual CLBs functions as if it includes M times N effective CLBs.
Inventors
- 👤 Steven M. Trimberger
- 👤 Richard A. Carberry
- 👤 Robert Anders Johnson
- 👤 Jennifer Wong
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-06 17:28
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17748; H03K19/1776; G; G06; G06F; G06F15/00; G06F15/76; G06F15/78; G06F15/7867; G06F30/00; G06F30/30; G06F30/34; H03K19/17704
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
77 words
A programmable logic device comprising: at least one configurable logic block, wherein each configurable logic block includes a combinational element and a sequential logic element; a plurality of programmable logic elements for configuring said at least one configurable logic block, wherein at least one programmable logic element includes a plurality of memory cells for configuring said combinational element and at least one programmable logic element includes a plurality of memory cells for configuring said sequential logic element.
Claim 2
Dependent Claim
24 words
The programmable logic device of Claim 1 further including a storage device for storing a plurality of intermediate states of one configurable logic block.
Claim 3
Dependent Claim
23 words
The programmable logic device of Claim 2 wherein each configurable logic block further includes a plurality of selectors for accessing said intermediate states.
Claim 4
Dependent Claim
30 words
The programmable logic device of Claim 2 or 3 wherein each configurable logic block further includes a plurality of selectors for accessing values in at least one configurable logic block.
Claim 5
Dependent Claim
17 words
The programmable logic device of Claim 4 wherein said values are output signals of sequential logic elements.
Claim 6
Dependent Claim
16 words
The programmable logic device of Claim 4 wherein said values are output signals of combinational elements.
Claim 7
Dependent Claim
23 words
The programmable logic device of any one of Claims 2 to 6 wherein said storage device is controlled by a first trigger signal.
Claim 8
Dependent Claim
23 words
The programmable logic device of any one of Claim 3 to 7 wherein said selectors are controlled by a plurality of trigger signals.
Claim 9
Dependent Claim
61 words
The programmable logic device of any one of Claims 2 to 8 further including a plurality of latches, wherein each bit of said storage device is provided to an associated latch, wherein the output terminals of said plurality of latches are coupled to the input terminals of a multiplexer, wherein said multiplexer is controlled by said plurality of programmable logic elements.
Claim 10
Dependent Claim
19 words
The programmable logic device of Claim 9 wherein said plurality of latches are clocked by a first trigger signal.
Claim 11
Dependent Claim
28 words
The programmable logic device of Claim 10 wherein said storage device is controlled by a plurality of trigger signals having a lower precision than said first trigger signal.
Claim 12
Dependent Claim
36 words
The programmable logic device of Claim 10 further including a bypass latch coupled between said configurable logic block and said multiplexer, wherein said bypass latch is controlled by the same trigger as said plurality of latches.
Claim 13
Dependent Claim
31 words
The programmable logic device of any one of Claims 4 to 12 Wherein each selector includes a first multiplexer for receiving signals from said configurable logic block and said storage device.
Claim 14
Dependent Claim
36 words
The programmable logic device of Claim 2 further including a multiplexer in at least one configurable logic block for selectively providing a signal from the sequential logic element or the combinational element to said storage device.
Claim 15
Dependent Claim
35 words
The programmable logic device of any preceding Claim further including a latch for providing a value of one of said plurality of memory cells as an output signal of one of said programmable logic elements.
Claim 16
Dependent Claim
24 words
The programmable logic device of Claim 2 wherein each configurable logic block further includes an output multiplexer for receiving signals from said storage device.
Claim 17
Dependent Claim
26 words
The programmable logic device of Claim 2 wherein said storage device is coupled to the input terminal of at least one of said configurable logic blocks.
Claim 18
Dependent Claim
21 words
The programmable logic device of any preceding Claim further including a plurality of lines for accessing said plurality of memory cells.
Claim 19
Dependent Claim
26 words
The programmable logic device of Claim 18 further including means for selecting a predetermined set of said plurality of programmable logic elements associated with one configuration.
Claim 20
Dependent Claim
32 words
The programmable logic device of Claim 18 further including a register for selecting a predetermined set of said plurality of programmable logic elements associated with one configuration within one configurable logic block.
Claim 21
Dependent Claim
78 words
A programmable logic device comprising: a configurable logic block including a combinational element and a sequential logic element; an input/output block; an interconnect structure for interconnecting said configurable logic block and said input/output block; a plurality of programmable logic elements for configuring said configurable logic block and said interconnect structure, wherein at least one programmable logic element includes a plurality of memory cells; and a storage device for storing a plurality of intermediate states of said input/output block.
Claim 22
Dependent Claim
85 words
A programmable logic device comprising: at least one configurable element; an interconnect structure for interconnecting said at least one configurable element; and a plurality of programmable logic elements for configuring said at least one configurable element, wherein at least one programmable logic element includes a plurality of memory cells for configuring said at least one configurable element, the device comprising a latch for providing a value of one of said plurality of memory cells as an output signal of one of said programmable logic elements.
Claim 23
Dependent Claim
54 words
A programmable logic device according to claim 22, comprising a plurality of memory cells for configuring said at least one configurable element, and wherein the number of said plurality of memory cells in a first programmable logic element differs from the number of said plurality of memory cells in a second programmable logic element.
References Cited (Backward Citations)
US4750155A
Cited
US4821233A
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