EP0785630A2
Expired / Lapsed
EP
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Time multiplexing in field programmable gate arrays
Assignee: HP Inc
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Filing: 1996-12-13
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Granted: —
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Expires: 2016-12-13
Abstract
Abstract A field programmable gate array (FPGA) system for time multiplexing a plurality of programmable configurations of the FPGA. The system includes a plurality of configuration memory cells which are loaded with configuration information. A time slice selector [15] couples selected configuration memory cells [12] to programmable switch elements [11] that determine the configuration and function of the logic within the FPGA. A time slice controller [19] determines which of the configuration memory cells the time slice selector [15] couples to the programmable switch elements [11]. The configuration memory cells may be implemented with half SRAM cells and the time slice selector [15] may be implemented with P-channel transistors.
Inventors
- 👤 Charles M.C. Tan
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-06 18:03
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17748; H03K19/17752; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/417; G11C11/419; H03K19/1733; H03K19/1737; H03K19/17704; H03K19/17756; H03K19/1776
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
104 words
A memory system for time multiplexing between a plurality of settings of a programmable switch element [11] within a FPGA, the system comprising: a plurality of memory cells [12] storing predetermined settings of the programmable switch element [11]; a time slice selector [15] receiving an output from each of the plurality of memory cells [12] and selecting one of the outputs from the memory cells [12] to drive the programmable switch element [11]; and a time slice controller [19] controlling the time slice selector [15] and determining which of the plurality of memory cells [12] is selected to drive the programmable switch element [11].
Claim 2
Dependent Claim
44 words
A memory system within a FPGA as recited in claim 1 further comprising a plurality of programmable switch elements wherein at least one of the programmable switch elements has a plurality of memory cells storing predetermined configurations of at least one programmable switch element.
Claim 3
Dependent Claim
34 words
The memory system as recited in claim 1 or 2, wherein the programmable switch element [11] is one of a cross point switch [21], a look up table input or a multiplexer control input.
Claim 4
Dependent Claim
32 words
The memory system as recited in claim 1, 2 or 3, wherein at least one of the memory cells comprise a half static random access memory cell, or a standard SRAM cell.
Claim 5
Dependent Claim
62 words
The memory system as recited in any preceding claim, wherein the time slice selector [15] comprises a plurality of P-channel transistors wherein each P-channel transistor of the plurality of P-channel transistors corresponds with a different one of the plurality of memory cells and wherein a memory cell determines the setting of a corresponding programmable switch element [11] by the corresponding P-channel transistor.
Claim 6
Dependent Claim
35 words
The memory system as recited in any preceding claim, wherein the time slice controller [19] is connected to a user provided clock which clocks the time slice controller [19] through a predetermined number of states.
Claim 7
Dependent Claim
18 words
The memory system as recited in claim 5, wherein the time slice selector [15] comprises a shift register.
Claim 8
Dependent Claim
28 words
The memory system as recited in claim 1, wherein a level shifter [17] ensures that the programmable switch element [11] is fully set to one of two states.
Claim 9
Dependent Claim
27 words
The memory system as recited in claim 1, wherein a pipeline synchronizer allows the settings of the programmable switch elements to be synchronized to a synchronization clock.
Claim 10
Independent Claim
62 words
A method for time multiplexing between a plurality of settings of a programmable switch element [11] within a FPGA, the method comprising the steps of: storing predetermined settings of the programmable switch element [11] within a plurality of memory cells [12]; and selecting an output from the one of the plurality of memory cells [12] to drive the programmable switch element [11].
References Cited (Backward Citations)
No citation records indexed.
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