Circuit and method of configuring a field programmable gate array

Claim 2

A circuit for configuring a plurality of field programmable gate arrays (FPGA), comprising: a first memory providing a data word at an output in response to an address signal; a first shift register having a data input, a clock input and a serial output, said data input being coupled for receiving said data word, said clock input being coupled for receiving a clock signal; a first FPGA having a data input, an enable input, a done output, and a clock output, said data input being coupled to said serial output of said first shift register, said enable input being coupled for receiving a start signal, said clock output providing said clock signal to said first shift register when enabled by said start signal, said done output providing a logic signal indicating completion of loading configuration data into said first FPGA; and a second FPGA having a data input, an enable input, a done output, and a clock output, said data input being coupled to said serial output of said first shift register, said enable input being coupled to said done output of said first FPGA, said clock output providing said clock signal to said first shift register when enabled by said logic signal from said done output of said first FPGA.

Claim 3

The circuit of claim 1 wherein said second FPGA further includes a done output for providing a logic signal indicating completion of loading configuration data into said second FPGA.

Claim 4

The circuit of claim 2 further including a third FPGA having a data input, an enable input, a done output, and a clock output, said data input being coupled to said serial output of said first shift register, said enable input being coupled to said done output of said second FPGA, said clock output providing said clock signal to said first shift register when enabled by said logic signal from said done output of said second FPGA.

Claim 5

The circuit of claim 3 further including a first counter having a clock input, a count output, and a load output, said clock input being coupled for receiving a system clock signal, said count output providing said address signal to said first memory, said load output providing a load control signal of said first shift register.

Claim 6

The circuit of claim 2 wherein said first FPGA includes: a latch having a set input, a reset input, and an output, said set input being coupled for receiving said start signal, said reset input being coupled for receiving said logic signal indicating completion of loading configuration data into said first FPGA; an oscillator having an output for providing an oscillator signal; and a tri-state buffer having an input, an enable input and an output, said input being coupled to said output of said oscillator, said enable input being coupled to said output of said latch, said output providing said clock signal of said first FPGA.

Claim 7

The circuit of claim 5 wherein said first FPGA further includes: a second shift register having an input coupled to said data input of said first FPGA and having a clock input coupled for receiving said clock signal of said first FPGA; a second memory having an input coupled to an output of said second shift register; and a first counter having a clock input, a count output, and a done output, said clock input being coupled for receiving said clock signal of said first FPGA, said count output providing an address signal to said second memory, said done output providing said logic signal indicating completion of loading configuration data into said first FPGA.

Claim 8

The circuit of claim 6 wherein said first FPGA further includes: a first NAND gate having first and second input coupled for receiving logic signals; a switching transistor having a gate, a drain and a source, said drain being coupled to an output of said first NAND gate, said gate being coupled to an output of said second memory; and a second NAND gate having an input coupled to said source of said switching transistor.

Claim 9

A field programmable gate array (FPGA) configuration circuit, comprising: a first memory providing a data word at an output in response to an address signal; a first shift register having a data input, a clock input and a serial output, said data input being coupled for receiving said data word, said clock input being coupled for receiving a clock signal; and a plurality of FPGAs each having a data input, an enable input, a done output, and a clock output, where said data input of a first FPGA is coupled to said serial output of said first shift register, and said enable input of said first FPGA is coupled for receiving a start signal, and said clock output of said first FPGA provides said clock signal to said first shift register when enabled by said start signal, and said done output of said first FPGA provides a logic signal indicating completion of loading configuration data into said first FPGA, and where said data input of a second FPGA is coupled to said serial output of said first shift register, and said enable input of said second FPGA is coupled to said done output of said first FPGA, and said clock output of said second FPGA provides said clock signal to said first shift register when enabled by said logic signal from said done output of said first FPGA.

Claim 10

A field programmable gate array (FPGA) configuration circuit, comprising: a first memory providing a data word at an output in response to an address signal; a first shift register having a data input, a clock input and a serial output, said data input being coupled for receiving said data word, said clock input being coupled for receiving a clock signal; and a plurality of FPGAs each having a data input, an enable input, a done output, and a clock output, where said data input of a first FPGA is coupled to said serial output of said first shift register, and said enable input of said first FPGA is coupled for receiving a start signal, and said clock output of said first FPGA provides said clock signal to said first shift register when enabled by said start signal, and said done output of said first FPGA provides a logic signal indicating completion of loading configuration data into said first FPGA, and where said data input of a second FPGA is coupled to said serial output of said first shift register, and said enable input of said second FPGA is coupled to said done output of said first FPGA, and said clock output of said second FPGA provides said clock signal to said first shift register when enabled by said logic signal from said done output of said first FPGA.

Claim 11

The FPGA configuration circuit of claim 8 wherein said second FPGA further includes a done output for providing a logic signal indicating completion of loading configuration data into said second FPGA.

Claim 12

The FPGA configuration circuit of claim 9 wherein said plurality of FPGAs further includes a third FPGA having a data input, an enable input, a done output, and a clock output, said data input being coupled to said serial output of said first shift register, said enable input being coupled to said done output of said second FPGA, said clock output providing said clock signal to said first shift register when enabled by said logic signal from said done output of said second FPGA.

Claim 13

The circuit of claim 10 further including a first counter having a clock input, a count output, and a load output, said clock input being coupled for receiving a system clock signal, said count output providing said address signal to said first memory, said load output providing a load control signal of said first shift register.

Claim 14

The FPGA configuration circuit of claim 9 wherein said first FPGA includes: a latch having a set input, a reset input, and an output, said set input being coupled for receiving said start signal, said reset input being coupled for receiving said logic signal indicating completion of loading configuration data into said first FPGA; an oscillator having an output for providing an oscillator signal; and a tri-state buffer having an input, an enable input and an output, said input being coupled to said output of said oscillator, said enable input being coupled to said output of said latch, said output providing said clock signal of said first FPGA.

Claim 15

The FPGA configuration circuit of claim 12 wherein said first FPGA further includes: a second shift register having an input coupled to said data input of said first FPGA and having a clock input coupled for receiving said clock signal of said first FPGA; a second memory having an input coupled to an output of said second shift register; and a first counter having a clock input, a count output, and a done output, said clock input being coupled for receiving said clock signal of said first FPGA, said count output providing an address signal to said second memory, said done output providing said logic signal indicating completion of loading configuration data into said first FPGA.

Claim 16

The FPGA configuration circuit of claim 13 wherein said first FPGA further includes: a first NAND gate having first and second input coupled for receiving logic signals; a switching transistor having a gate, a drain and a source, said drain being coupled to an output of said first NAND gate, said gate being coupled to an output of said second memory; and a second NAND gate having an input coupled to said source of said switching transistor.

Claim 19

The method of claim 15 further including the step of generating a done signal from said second FPGA indicating completion of loading configuration data from said serial data stream into said second FPGA.

Claim 20

The method of claim 16 further including the steps of: enabling a third oscillator signal in a third FPGA to act as said clock signal upon receiving said done signal from said second FPGA; and disabling said second oscillator signal in said second FPGA.

Claim 21

The method of claim 17 further including the step of storing said serial data stream into a memory storage location of said third FPGA in response to said clock signal from said third FPGA.

Claim 22

The method of claim 18 further including the steps of: generating a done signal from said third FPGA indicating completion of loading configuration data from said serial data stream into said third FPGA; and disabling said third oscillator signal in said third FPGA.