EP0746106A2
Expired / Lapsed
EP
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Programmable array I/O - routing resource
Assignee: International Business Machines Corp
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Filing: 1996-05-07
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Granted: —
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Expires: 2016-05-07
Abstract
Abstract A programmable array having programmable logic cells, a programmable interconnect network and a programmable I/O system. Two I/O interfaces are provided for respective logic cells about the perimeter of the array. The I/O interfaces comprise input, output and enable paths. Each of these paths has an associated multiplexer. An I/O routing network is positioned about the perimeter of the array. Conductors connecting the I/O interface multiplexers to the programmable interconnect network also intersect, and can be programmably connected to, buses of the I/O routing network.
Inventors
- 👤 Allan Robert Bertolet
- 👤 Scott Whitney Gould
- 👤 Kenneth Ferguson
- 👤 Eric Ernest Millham
- 👤 Ronald Raymond Palmer
- 👤 Terrance John Zittritsch
- 👤 Brian Worth
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-07 11:37
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17736; H03K19/1733; H03K19/1737; H03K19/17704
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
245 words
A programmable array having a plurality of programmable logic cells arrayed therein, said programmable array further comprising: a programmable interconnect network, the programmable interconnect network comprising a first plurality of buses wherein selected buses in the first plurality of buses are connectable to ones of the plurality of logic cells, the first plurality of buses including a plurality of switches, each switch of the plurality of switches for programmably providing signals between buses of the first plurality of buses; and a first I/O interface associated with a corresponding one of the plurality of logic cells, the first I/O interface comprising: a data output path for carrying array output signals to an I/O terminal corresponding to the first I/O interface; a data input path for carrying array input signals from the I/O terminal corresponding to the first I/O interface; a first multiplexer having an output connected to said data output path, said first multiplexer further having a plurality of inputs; a second multiplexer having an input connected to said data input path, said second multiplexer further having a plurality of outputs; and first and second I/O signal buses, the first I/O signal bus being connected between one of the switches of the first plurality of buses and one of the plurality of inputs of the first multiplexer, the second I/O signal bus being connected between one of the switches of the first plurality of buses and one of the plurality of outputs of the second multiplexer.
Claim 2
Dependent Claim
56 words
The programmable array of claim 1 further comprising: a plurality of I/O routing buses, said plurality of I/O routing buses running proximate said first I/O interface, at least one of said plurality of I/O routing buses being programmably connectable to at least one of the first and second I/O signal buses of the first I/O interface.
Claim 3
Dependent Claim
42 words
The programmable array of claim 2 further comprising a programmable element connected between the at least one of said plurality of I/O routing buses and the at least one of the first and second I/O signal buses of the first I/O interface.
Claim 4
Dependent Claim
21 words
The programmable array of claim 2 wherein the plurality of I/O routing buses runs generally along a perimeter of the array.
Claim 5
Dependent Claim
110 words
The programmable array of claim 1 wherein said first I/O interface further comprises: an enable path for providing enable signals to said data output path such that said array output signals can be controllably provided to the I/O terminal corresponding to the first I/O interface; a third multiplexer having an output connected to said enable path of the first I/O interface, said third multiplexer further having a plurality of inputs; and a third I/O signal bus, the third I/O signal bus being connected between one of the switches of said first plurality of buses and one of the plurality of inputs of the third multiplexer of the first I/O interface.
Claim 6
Dependent Claim
52 words
The programmable array of claim 5 wherein the first I/O signal bus of said first I/O interface is connected to one of the plurality of outputs of the second multiplexer of the first I/O interface and to one of the plurality of inputs of the third multiplexer of the first I/O interface.
Claim 7
Dependent Claim
52 words
The programmable array of claim 5 wherein the second I/O signal bus of the first I/O interface is connected to one of the plurality of inputs of the first multiplexer of the first I/O interface and to one of the plurality of inputs of the third multiplexer of the first I/O interface.
Claim 8
Dependent Claim
52 words
The programmable array of claim 5 wherein the third I/O signal bus of the first I/O interface is connected to one of the plurality of inputs of the first multiplexer of the first I/O interface and to one of the plurality of outputs of the second multiplexer of the first I/O interface.
Claim 9
Dependent Claim
32 words
The programmable array of claim 5 wherein the first, second and third I/O signal buses are all connected to each of the first, second, and third multiplexers of the first I/O interface.
Claim 10
Dependent Claim
48 words
The programmable array of claim 9 wherein the corresponding one of the plurality of logic cells includes: a first conductor connected to an input of the first multiplexer of the first I/O interface; and a second conductor connected to the data input path of the first I/O interface.
Claim 11
Dependent Claim
35 words
The programmable array of claim 1 wherein the first I/O signal bus of the first I/O interface is connected to one of the plurality of outputs of the second multiplexer of the first I/O interface.
Claim 12
Dependent Claim
35 words
The programmable array of claim 1 wherein the second I/O signal bus of the first I/O interface is connected to one of the plurality of inputs of the first multiplexer of the first I/O interface.
Claim 13
Dependent Claim
48 words
The programmable array of claim 1 wherein the corresponding one of the plurality of logic cells includes: a first conductor connected to an input of the first multiplexer of the first I/O interface; and a second conductor connected to the data input path of the first I/O interface.
Claim 14
Dependent Claim
240 words
The programmable array of claim 1 wherein the programmable interconnect network further comprises a second plurality of buses wherein selected buses in the second plurality of buses are connectable to the ones of the plurality of logic cells, the second plurality of buses including a second plurality of switches, each switch of the second plurality of switches for programmably providing signals between buses of the second plurality of buses, wherein the programmable array further comprises: a second I/O interface associated with the corresponding one of the plurality of logic cells, the second I/O interface comprising: a data output path for carrying array output signals to an I/O terminal corresponding to the second I/O interface; a data input path for carrying array input signals from the I/O terminal corresponding to the second I/O interface; a first multiplexer having an output connected to said data output path, said first multiplexer further having a plurality of inputs; a second multiplexer having an input connected to said data input path, said second multiplexer further having a plurality of outputs; and first and second I/O signal buses, the first I/O signal bus being connected between one of the switches of the second plurality of buses and one of the plurality of inputs of the first multiplexer, the second I/O signal bus being connected between one of the switches of the second plurality of buses and one of the plurality of outputs of the second multiplexer.
Claim 15
Dependent Claim
109 words
The programmable array of claim 14 wherein the second I/O interface further comprises: an enable path for providing enable signals to said data output path such that said array output signals can be controllably provided to the I/O terminal corresponding to the second I/O interface; a third multiplexer having an output connected to said enable path of the second I/O interface, said third multiplexer having a plurality of inputs; and a third I/O signal bus, the third I/O signal bus being connected between one of the switches of said second plurality of buses and one of the plurality of inputs of the third multiplexer of the second I/O interface.
Claim 16
Dependent Claim
94 words
The programmable array of claim 15 wherein the corresponding one of the plurality of logic cells includes: a first conductor connected to an input of one of the first and third multiplexers of the first I/O interface and connected to an input of one of the first and third multiplexers of the second I/O interface; and a second conductor connected to an input of one of the first and third multiplexers of the first I/O interface and connected to an input of one of the first and third multiplexers of the second I/O interface.
Claim 17
Dependent Claim
46 words
The programmable array of claim 16 wherein the corresponding one of the plurality of logic cells includes: a third conductor connected to the data input path of the first I/O interface; and a fourth conductor connected to the data input path of the second I/O interface.
Claim 18
Dependent Claim
60 words
The programmable array of claim 14 further comprising: a plurality of I/O routing buses, said plurality of I/O routing buses running proximate said first and second I/O interfaces, at least one of said plurality of I/O routing buses being programmably connectable to at least one of the first and second I/O signal buses of the first and second I/O interfaces.
Claim 19
Dependent Claim
43 words
The programmable array of claim 18 further comprising programmable elements connected between the at least one of the plurality of I/O routing buses and the at least one of the first and second I/O signal buses of the first and second I/O interfaces.
Claim 20
Dependent Claim
21 words
The programmable array of claim 18 wherein the plurality of I/O routing buses runs generally along a perimeter of the array.
Claim 21
Dependent Claim
72 words
The programmable array of claim 19 wherein at least one of said programmable elements comprises a programmable switching repeater having four ports, each port being connected to a different bus of said plurality of I/O routing buses such that a signal received at a first one of said ports of the programmable switching repeater can be programmably buffered and redriven to a second one of said ports of the programmable switching repeater.
References Cited (Backward Citations)
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