Field programmable gate array with multi-port RAM

Claim 1

An integrated circuit including a field programmable gate array (FPGA) which includes a programmable function unit (PFU), comprising: first and second programmable elements for generating various functions including first and second respective RAM cells (102, 108) in response to a configuration bit stream; and a programmable switching device (114) responsive to the configuration bit stream for providing bit-level coupling between the RAM cells so that the RAM cells together provide a multi-port RAM cell.

Claim 6

A method of programming and operating a field programmable gate array (FPGA) including a plurality of programmable function units (PFUs) and a programmable interconnection network, comprising the steps of: applying a configuration bit stream to the FPGA for instructing a first PFU to function as a first set of RAM cells (102) coupled to a first read/write port (104) and as a second set of RAM cells (108) coupled to a second read/write port (110), and for instructing switching devices (114) in the first PFU to provide bit-level coupling between pairs of the RAM cells so that each RAM cell is a member of one coupled pair, with each coupled pair including one RAM cell from the first set of RAM cells and one RAM cell from the second set of RAM cells, wherein each coupled pair provides a dual-port RAM cell that is accessible by both the first and second read/write ports; writing data through the first read/write port into at least one dual-port RAM cell; and reading data through the second read/write port from at least one dual-port RAM cell.