US5631577A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Synchronous dual port RAM
Assignee: Xilinx Inc
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Filing: 1996-06-21
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Granted: 1997-05-20
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Expires: 2016-06-21
Abstract
Abstract A configurable logic block (CLB) in the dual port mode uses one address to write the same information in a first RAM and a second RAM. The input signals provided to the second function generator can be used to read, independently from and even asynchronously with, the write operation, thereby dramatically increasing the speed of applications using the two sets of RAM. A CLB in the synchronous mode latches the appropriate address and data signals, and generates a strobed write enable signal. The strobed signal is self-timed, i.e. the write operation is fully automatic, thereby ensuring that a write operation occurs within one clock cycle.
Inventors
- 👤 Philip M. Freidin
- 👤 Edmond Y. Cheung
- 👤 Charles R. Erickson
- 👤 Tsung-Lu Syu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 09:01
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/1733; H03K19/1735; H03K19/1736; G; G11; G11C; G11C7/00; G11C7/10; G11C7/1072; G11C7/22; G11C8/00; G11C8/16; H03K19/177; H03K19/17704
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
77 words
A structure for a programmable logic device comprising: a first logic generator having a Read Address terminal and a Write Address Terminal; a second logic generator having a Read Address terminal and a Write Address Terminal; addressing circuitry coupled to said Read and Write Address terminals of said first and second logic generators, wherein a control signal provided to said addressing circuitry provides a signal to the Write Address terminals of said first and second logic generators.
Claim 2
Dependent Claim
77 words
A structure for a programmable logic device comprising: a first logic generator having a Read Address terminal and a Write Address Terminal; a second logic generator having a Read Address terminal and a Write Address Terminal; addressing circuitry coupled to said Read and Write Address terminals of said first and second logic generators, wherein a control signal provided to said addressing circuitry provides a signal to the Write Address terminals of said first and second logic generators.
Claim 3
Dependent Claim
17 words
The structure of claim 1 wherein said addressing circuitry includes a multiplexer which selectively provides said signal.
Claim 4
Dependent Claim
28 words
The structure of claim 2 wherein said addressing circuitry further includes a first latch coupled between said multiplexer and said Write Address terminal of said first logic generator.
Claim 5
Dependent Claim
29 words
The structure of claim 3 wherein said addressing circuitry further includes a second latch coupled between said addressing circuitry and said Write Address terminal of said second logic generator.
Claim 6
Dependent Claim
33 words
The structure of claim 2 wherein said addressing circuitry includes a first address decoder for providing a first input signal to said multiplexer and said Read Address terminal of said first logic generator.
Claim 7
Dependent Claim
33 words
The structure of claim 5 wherein said addressing circuitry includes a second address decoder for providing a second input signal to said multiplexer and said Read Address terminal of said second logic generator.
Claim 8
Dependent Claim
94 words
A configurable logic block configuration comprising: a first set of random access memory cells; a second set of random access memory cells; first addressing means for providing a first Read address signal to address one of said first set of random access memory cells; second addressing means for providing a second Read address signal to address one of said second set of random access memory cells; and means for selectively providing said first Read signal or said second Read address signal to write to one of said first set of random access memory cells.
Claim 9
Dependent Claim
94 words
A configurable logic block configuration comprising: a first set of random access memory cells; a second set of random access memory cells; first addressing means for providing a first Read address signal to address one of said first set of random access memory cells; second addressing means for providing a second Read address signal to address one of said second set of random access memory cells; and means for selectively providing said first Read signal or said second Read address signal to write to one of said first set of random access memory cells.
Claim 10
Dependent Claim
16 words
The configurable logic block of claim 7 wherein said means for selectively providing includes a multiplexer.
Claim 11
Dependent Claim
25 words
The configurable logic block of claim 8 wherein said first addressing means includes an address decode circuit coupled to an input terminal of said multiplexer.
Claim 12
Dependent Claim
25 words
The configurable logic block of claim 8 wherein said second addressing means includes an address decode circuit coupled to an input terminal of said multiplexer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-05-19 | 2000-11-18 | 2001-05-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-05-19 | 2004-11-18 | 2005-05-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-05-19 | 2008-11-18 | 2009-05-20 | $7700.00 | Window Closed / Lapsed |