Patent US5814889A successfully refreshed from Google Patents.
US5814889A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Intergrated circuit with coaxial isolation and method
Assignee: Intersil Americas LLC
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Filing: 1995-06-05
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Granted: 1998-09-29
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Expires: 2015-06-05
Abstract
Abstract A die 810 has an outer, annular via 814 filled with conductive material in order to electrically shield an inner via 816. A die 820 can be electrically shielded from another area 822 by use of a wall 823 having a trench with oxidized side walls and a conductive filling.
Inventors
- 👤 Stephen Joseph Gaul
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 15:40
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/01; H10W10/041; H10W10/40; H10W20/00; H10W20/01; H10W20/021; H10W20/023; H10W20/0234; H10W20/0238; H10W20/0245; H10W20/20; H10W20/211; H10W20/216; H10W72/00; H10W72/50; H10W72/551; H10W72/552; H10W72/851; H10W72/874; H10W72/884; H10W90/00; H10W90/701; H10W90/751; H10W90/754
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
148 words
An integrated circuit with a coaxial via comprising: a wafer of semiconductor material with first and second surfaces and with integrated circuits formed on the first surface of said wafer; a first via comprising inner and outer walls spaced from each other and extending from a first open end on the first surface of the wafer to a second open end on the second surface of the second surface, said inner wall of said first via enclosing a portion of said wafer; a second via in the portion of the wafer enclosed by said inner wall of said first via, said second via having a first open end on the first surface of the wafer, an elongated, open passage extending to a second open end of the via on the second surface a dielectric surface on each wall of the vias; and a conductive material filling said vias.
Claim 2
Dependent Claim
148 words
An integrated circuit with a coaxial via comprising: a wafer of semiconductor material with first and second surfaces and with integrated circuits formed on the first surface of said wafer; a first via comprising inner and outer walls spaced from each other and extending from a first open end on the first surface of the wafer to a second open end on the second surface of the second surface, said inner wall of said first via enclosing a portion of said wafer; a second via in the portion of the wafer enclosed by said inner wall of said first via, said second via having a first open end on the first surface of the wafer, an elongated, open passage extending to a second open end of the via on the second surface a dielectric surface on each wall of the vias; and a conductive material filling said vias.
Claim 3
Dependent Claim
22 words
The integrated circuit of claim 1 wherein the conductive material is one selected from the group consisting of doped polysilicon and tungsten.
Claim 4
Dependent Claim
103 words
An integrated circuit with digital and analog circuits comprising: a wafer of semiconductor material with first and second surfaces and with said analog circuits formed in a first area of the first surface of said wafer and with said digital circuits formed in a second area of the first surface of said wafer; a trench for electrically separating the first area from the second area, said trench having spaced apart side walls extending from the first surface of the wafer to the second surface of the wafer; a dielectric coating on said trench sidewalls; a conductive material filling said trench between said sidewalls.
Claim 5
Dependent Claim
103 words
An integrated circuit with digital and analog circuits comprising: a wafer of semiconductor material with first and second surfaces and with said analog circuits formed in a first area of the first surface of said wafer and with said digital circuits formed in a second area of the first surface of said wafer; a trench for electrically separating the first area from the second area, said trench having spaced apart side walls extending from the first surface of the wafer to the second surface of the wafer; a dielectric coating on said trench sidewalls; a conductive material filling said trench between said sidewalls.
Claim 6
Dependent Claim
22 words
The integrated circuit of claim 3 wherein the conductive material is one selected from the group consisting of metal and doped polysilicon.
Claim 7
Dependent Claim
19 words
The integrated circuit of claim 3 wherein the conductive material filling the trench is coupled to a reference potential.
Claim 8
Dependent Claim
12 words
The integrated circuit of claim 5 wherein the reference potential is ground.
References Cited (Backward Citations)
US3462650A
Cited
US3256465A
Cited
US3343256A
Cited
US3456335A
Cited
US3372070A
Cited
US3418545A
Cited
US3454835A
Cited
US3445686A
Cited
US3648131A
Cited
US3798513A
Cited
US3796927A
Cited
US3885196A
Cited
US3982268A
Cited
US3959579A
Cited
US3969745A
Cited
US4074342A
Cited
US3962052A
Cited
US4097890A
Cited
US4104674A
Cited
US4188709A
Cited
US4275410A
Cited
US4263341A
Cited
US4368503A
Cited
US4528072A
Cited
US4379307A
Cited
US4467343A
Cited
US4720738A
Cited
US4761681A
Cited
US4613891A
Cited
US4670764A
Cited
US4612083A
Cited
US4935800A
Cited
US4897708A
Cited
US4954875A
Cited
US4701424A
Cited
US4839510A
Cited
JPS6450543A
Cited
US4982266A
Cited
US4839309A
Cited
US4862322A
Cited
JPH03232239A
Cited
US5057895A
Cited
US5198695A
Cited
US5317183A
Cited
US5196920A
Cited
US5268326A
Cited
US5363550A
Cited
US5421083A
Cited
US5475255A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-09-28 | 2002-03-30 | 2002-09-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-09-28 | 2006-03-30 | 2006-09-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-09-28 | 2010-03-30 | 2010-09-29 | $7700.00 | Window Closed / Lapsed |