US5317183A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Substrate noise coupling reduction for VLSI applications with mixed analog and digital circuitry
Assignee: International Business Machines Corp
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Filing: 1991-09-03
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Granted: 1994-05-31
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Expires: 2011-09-03
Abstract
Abstract The internal electrical noise generated by circuits of a VLSI chip is controlled by separating the logic circuit substrate contacts from the logic circuits ground contacts. A separate return path interconnects each contact to card ground. Further noise reduction is achieved by providing a void region between the noise generating devices and the "quiet" devices. A substrate contact ring is provided in the void region. The substrate contact ring is connected by a separate path to card ground.
Inventors
- 👤 Charles R. Hoffman
- 👤 John M. Mullen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 04:15
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/003; H03K19/00346; G; G06; G06F; G06F11/00; H10; H10D; H10D89/00
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
131 words
An improved VLSI chip comprising: a substrate; a plurality of interconnected digital devices which generate digital functions fabricated on said substrate; circuit means for generating analog functions fabricated on said substrate; at least one device contact are for coupling to at least one digital device fabricated in said substrate; a device ground pin (C D -GND) coupled to the chip; a first conductive means for forming a device ground return path interconnecting the device ground pin (C D -GND) and the at least one device contact area; a substrate contact region fabricated on the substrate; a substrate ground pin (C S -GND) coupled to the chip; and a second conductive means for forming a substrate ground return path interconnecting the substrate ground pin (C S -GND) and the substrate contact region.
Claim 2
Dependent Claim
131 words
An improved VLSI chip comprising: a substrate; a plurality of interconnected digital devices which generate digital functions fabricated on said substrate; circuit means for generating analog functions fabricated on said substrate; at least one device contact are for coupling to at least one digital device fabricated in said substrate; a device ground pin (C D -GND) coupled to the chip; a first conductive means for forming a device ground return path interconnecting the device ground pin (C D -GND) and the at least one device contact area; a substrate contact region fabricated on the substrate; a substrate ground pin (C S -GND) coupled to the chip; and a second conductive means for forming a substrate ground return path interconnecting the substrate ground pin (C S -GND) and the substrate contact region.
Claim 3
Dependent Claim
48 words
The improved VLSI chip of claim 1 further including a card for mounting the chip; a card ground pin (CARD GND) fabricated on said card; and third conductive means for forming a first chip to card conductive path interconnecting the card ground pin and the device ground pin.
Claim 4
Dependent Claim
35 words
The improved VLSI chip of claim 2 further including a fourth conductive means for forming a device ground return path interconnecting the device ground pin (C D -GND) to the card ground pin (CARD GND).
Claim 5
Dependent Claim
35 words
The improved VLSI chip of claim 1 further including an area on said chip in which no switching circuit components are fabricated separating the digital devices from the circuit means which generates the analog functions.
Claim 6
Dependent Claim
32 words
The improved VLSI chip of claim 4 wherein chip layout is such that the circuit means for generating the analog functions is located on the lower left corner of an analog macro.
Claim 7
Dependent Claim
18 words
The improved VLSI chip of claim 4 wherein the a substrate contact region is fabricated in the area.
Claim 8
Dependent Claim
20 words
The improved VLSI chip of claim 4 wherein the substrate contact region is positioned in the center of the area.
Claim 9
Dependent Claim
47 words
The improved VLSI chip of claim 6 further including a card for mounting the VLSI chip; a ground pin (CARD GND) fabricated on said card; and a fifth conductive means which establishes a return substrate ground path interconnecting the substrate contact region to the card ground pin.
Claim 10
Dependent Claim
47 words
The improved VLSI chip of claim 7 further including a card for mounting the VLSI chip; a ground pin (CARD GND) fabricated on the card; and a fifth conductive means which establishes a return substrate ground path interconnecting the substrate contact region to the card ground pin.
References Cited (Backward Citations)
US4672584A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-05-30 | 1997-11-29 | 1998-05-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-05-30 | 2001-11-29 | 2002-05-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-05-30 | 2005-11-29 | 2006-05-31 | $7700.00 | Window Closed / Lapsed |