US5814889A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Intergrated circuit with coaxial isolation and method
Assignee: Intersil Americas LLC
•
Filing: 1995-06-05
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Granted: 1998-09-29
•
Expires: 2015-06-05
Abstract
Abstract A die 810 has an outer, annular via 814 filled with conductive material in order to electrically shield an inner via 816. A die 820 can be electrically shielded from another area 822 by use of a wall 823 having a trench with oxidized side walls and a conductive filling.
Inventors
- 👤 Stephen Joseph Gaul
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 06:15
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/01; H10W10/041; H10W10/40; H10W20/00; H10W20/01; H10W20/021; H10W20/023; H10W20/0234; H10W20/0238; H10W20/0245; H10W20/20; H10W20/211; H10W20/216; H10W72/00; H10W72/50; H10W72/551; H10W72/552; H10W72/851; H10W72/874; H10W72/884; H10W90/00; H10W90/701; H10W90/751; H10W90/754
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
148 words
An integrated circuit with a coaxial via comprising: a wafer of semiconductor material with first and second surfaces and with integrated circuits formed on the first surface of said wafer; a first via comprising inner and outer walls spaced from each other and extending from a first open end on the first surface of the wafer to a second open end on the second surface of the second surface, said inner wall of said first via enclosing a portion of said wafer; a second via in the portion of the wafer enclosed by said inner wall of said first via, said second via having a first open end on the first surface of the wafer, an elongated, open passage extending to a second open end of the via on the second surface a dielectric surface on each wall of the vias; and a conductive material filling said vias.
Claim 2
Dependent Claim
148 words
An integrated circuit with a coaxial via comprising: a wafer of semiconductor material with first and second surfaces and with integrated circuits formed on the first surface of said wafer; a first via comprising inner and outer walls spaced from each other and extending from a first open end on the first surface of the wafer to a second open end on the second surface of the second surface, said inner wall of said first via enclosing a portion of said wafer; a second via in the portion of the wafer enclosed by said inner wall of said first via, said second via having a first open end on the first surface of the wafer, an elongated, open passage extending to a second open end of the via on the second surface a dielectric surface on each wall of the vias; and a conductive material filling said vias.
Claim 3
Dependent Claim
22 words
The integrated circuit of claim 1 wherein the conductive material is one selected from the group consisting of doped polysilicon and tungsten.
Claim 4
Dependent Claim
103 words
An integrated circuit with digital and analog circuits comprising: a wafer of semiconductor material with first and second surfaces and with said analog circuits formed in a first area of the first surface of said wafer and with said digital circuits formed in a second area of the first surface of said wafer; a trench for electrically separating the first area from the second area, said trench having spaced apart side walls extending from the first surface of the wafer to the second surface of the wafer; a dielectric coating on said trench sidewalls; a conductive material filling said trench between said sidewalls.
Claim 5
Dependent Claim
103 words
An integrated circuit with digital and analog circuits comprising: a wafer of semiconductor material with first and second surfaces and with said analog circuits formed in a first area of the first surface of said wafer and with said digital circuits formed in a second area of the first surface of said wafer; a trench for electrically separating the first area from the second area, said trench having spaced apart side walls extending from the first surface of the wafer to the second surface of the wafer; a dielectric coating on said trench sidewalls; a conductive material filling said trench between said sidewalls.
Claim 6
Dependent Claim
22 words
The integrated circuit of claim 3 wherein the conductive material is one selected from the group consisting of metal and doped polysilicon.
Claim 7
Dependent Claim
19 words
The integrated circuit of claim 3 wherein the conductive material filling the trench is coupled to a reference potential.
Claim 8
Dependent Claim
12 words
The integrated circuit of claim 5 wherein the reference potential is ground.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-09-28 | 2002-03-30 | 2002-09-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-09-28 | 2006-03-30 | 2006-09-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-09-28 | 2010-03-30 | 2010-09-29 | $7700.00 | Window Closed / Lapsed |