Patent US5808498A successfully refreshed from Google Patents.
US5808498A
Expired / Lapsed
US
⏱️ 0.0 years remaining
At frequency phase shifting circuit for use in a quadrature clock generator
Assignee: Rambus Inc
•
Filing: 1997-07-10
•
Granted: 1998-09-15
•
Expires: 2017-07-10
Abstract
Abstract A phase shifting circuit that may be used as part of a quadrature clock generator. The phase shifting circuit comprises a triangle wave generator coupled to receive an input reference signal. The triangle wave generator outputs a pair of complementary triangle wave signals in response to the input reference signal. A comparator having a pair of inputs is coupled to receive the pair of complementary triangle wave signals. The comparator outputs an output signal having a predetermined phase relationship with the input reference signal in response to a comparison between the pair of complementary triangle wave signals.
Inventors
- 👤 Kevin S. Donnelly
- 👤 Pak Shing Chau
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 12:37
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/081; H03L7/0812; H03H; H03H11/00; H03H11/02; H03H11/16; H03H11/18; H03K; H03K5/00; H03K5/13; H03K5/133; H03K5/15; H03K5/151; H03L7/0814; H03L7/0816; H03K2005/00013; H03K2005/0015; H03K2005/00195; H03K2005/00208
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
188 words
A phase shifting circuit comprising: a first differential amplifier including: a pair of field effect transistors configured to form a source coupled pair having a common node, and including a pair of inputs for receiving an input reference signal and complement thereof and a pair of output nodes; first and second current sources coupled respectively between the output nodes and a first supply rail, the first and second current sources sourcing a current value of I amperes: and a third current source coupled between the common node and a second supply rail, the third current source sinking a current value of 2I amperes; a filter circuit coupled across the output nodes, the filter circuit causing the output nodes of the differential amplifier to produce a pair of complementary triangle wave signals in response to the input reference signal and complement thereof; and a comparator having a pair of inputs coupled to receive the pair of complementary triangle wave signals, the comparator generating an output signal having a predetermined phase relationship with the input reference signal in response to a comparison between the pair of complementary triangle wave signals.
Claim 2
Dependent Claim
188 words
A phase shifting circuit comprising: a first differential amplifier including: a pair of field effect transistors configured to form a source coupled pair having a common node, and including a pair of inputs for receiving an input reference signal and complement thereof and a pair of output nodes; first and second current sources coupled respectively between the output nodes and a first supply rail, the first and second current sources sourcing a current value of I amperes: and a third current source coupled between the common node and a second supply rail, the third current source sinking a current value of 2I amperes; a filter circuit coupled across the output nodes, the filter circuit causing the output nodes of the differential amplifier to produce a pair of complementary triangle wave signals in response to the input reference signal and complement thereof; and a comparator having a pair of inputs coupled to receive the pair of complementary triangle wave signals, the comparator generating an output signal having a predetermined phase relationship with the input reference signal in response to a comparison between the pair of complementary triangle wave signals.
Claim 3
Dependent Claim
18 words
The phase shifting circuit of claim 1, wherein the phase shifting circuit is implemented as a CMOS circuit.
Claim 4
Dependent Claim
19 words
The phase shifting circuit of claim 1, wherein the phase shifting circuit is implemented on a single semiconductor substrate.
Claim 5
Dependent Claim
127 words
The phase shifting circuit of claim 1, wherein the comparator further outputs a complementary output signal, and wherein the phase shifting circuit further comprises: a duty cycle error measurement circuit configured to receive the output signal and the complementary output signal from the comparator, the duty cycle error measurement circuit generating a pair of error signals in response to the output signals of the comparator deviating from a 50% duty cycle; a second differential amplifier including a pair of inputs coupled to the pair of error signals and a pair of outputs coupled to the output nodes of the first differential amplifier, the second differential amplifier providing a correction current on one of its outputs such that the output of the comparator has a 50% duty cycle.
Claim 6
Dependent Claim
258 words
A quadrature clock generator circuit for generating a first output signal and a second output signal that is approximately 90 degrees out of phase with the first output signal, the clock generator circuit comprising: a first comparator having a pair of inputs coupled to a pair of complementary input reference signals, the first comparator generating the first output signal in response to the complementary input reference signals; a phase shifting circuit coupled to the complementary input reference signals, the phase shifting circuit comprising: (i) a first differential amplifier including: a pair of field effect transistors configured to form a source coupled pair having a common node, and including a pair of inputs for receiving the complementary input reference signals and a pair of output nodes: first and second current sources coupled respectively between the output nodes and a first supply rail, the first and second current sources sourcing a current value of I amperes: and a third current source coupled between the common node and a second supply rail, the third current source sinking a current value of 2I amperes; (ii) a filter circuit coupled across the output nodes, the filter circuit causing the output nodes of the differential amplifier to produce a pair of complementary triangle wave signals in response to the complementary input reference signals: and (iii) a second comparator having a pair of inputs coupled to receive the pair of complementary triangle wave signals, the second comparator outputting the second output signal in response to a comparison between the pair of complementary triangle wave signals.
Claim 7
Dependent Claim
258 words
A quadrature clock generator circuit for generating a first output signal and a second output signal that is approximately 90 degrees out of phase with the first output signal, the clock generator circuit comprising: a first comparator having a pair of inputs coupled to a pair of complementary input reference signals, the first comparator generating the first output signal in response to the complementary input reference signals; a phase shifting circuit coupled to the complementary input reference signals, the phase shifting circuit comprising: (i) a first differential amplifier including: a pair of field effect transistors configured to form a source coupled pair having a common node, and including a pair of inputs for receiving the complementary input reference signals and a pair of output nodes: first and second current sources coupled respectively between the output nodes and a first supply rail, the first and second current sources sourcing a current value of I amperes: and a third current source coupled between the common node and a second supply rail, the third current source sinking a current value of 2I amperes; (ii) a filter circuit coupled across the output nodes, the filter circuit causing the output nodes of the differential amplifier to produce a pair of complementary triangle wave signals in response to the complementary input reference signals: and (iii) a second comparator having a pair of inputs coupled to receive the pair of complementary triangle wave signals, the second comparator outputting the second output signal in response to a comparison between the pair of complementary triangle wave signals.
Claim 8
Dependent Claim
18 words
The quadrature clock generator of claim 5, wherein the quadrature clock generator is implemented as a CMOS circuit.
Claim 9
Dependent Claim
19 words
The quadrature clock generator of claim 5, wherein the quadrature clock generator is implemented on a single semiconductor substrate.
Claim 10
Dependent Claim
133 words
The quadrature clock generator of claim 5, wherein the second comparator further outputs a complementary output signal, and wherein the quadrature clock generator further comprises: a duty cycle error measurement circuit configured to receive the second output signal and the complementary output signal from the second comparator, the duty cycle error measurement circuit generating a pair of error signals in response to the output signals of the second comparator deviating from a 50% duty cycle; and a second differential amplifier including a pair of inputs coupled to the pair of error signals and a pair of outputs coupled to the output nodes of the first differential amplifier, the second differential amplifier providing a correction current on one of its outputs such that the output of the second comparator has a 50% duty cycle.
Claim 11
Dependent Claim
240 words
A delay-locked loop (DLL) comprising: a quadrature clock generator circuit for outputting a first output signal and a second output signal that is approximately 90 degrees out of phase with the first output signal, the clock generator circuit comprising: a first comparator having an input coupled to an input reference signal, the first comparator outputting the first output signal in response the input reference signal; a phase shifting circuit coupled to the input signal, the phase shifting circuit comprising: a triangle wave generator coupled to receive the input reference signal, the triangle wave generator including a pair of complementary outputs that output a pair of complementary triangle wave signals in response to the input reference signal; and a second comparator having a pair of inputs coupled to receive the pair of complementary triangle wave signals, the comparator outputting the second output signal in response to a comparison between the pair of complementary triangle wave signals; a variable delay circuit coupled to receive the first and second output signals, the variable delay circuit outputting a delayed signal in response to a control signal; a clock buffer circuit coupled to receive and buffer the delayed circuit, the clock buffer circuit outputting an output signal of the DLL; and a phase detector coupled to the input reference signal and the output signal of the DLL, the phase comparator generating the control signal in response to a comparison between the input and output signals.
Claim 12
Dependent Claim
240 words
A delay-locked loop (DLL) comprising: a quadrature clock generator circuit for outputting a first output signal and a second output signal that is approximately 90 degrees out of phase with the first output signal, the clock generator circuit comprising: a first comparator having an input coupled to an input reference signal, the first comparator outputting the first output signal in response the input reference signal; a phase shifting circuit coupled to the input signal, the phase shifting circuit comprising: a triangle wave generator coupled to receive the input reference signal, the triangle wave generator including a pair of complementary outputs that output a pair of complementary triangle wave signals in response to the input reference signal; and a second comparator having a pair of inputs coupled to receive the pair of complementary triangle wave signals, the comparator outputting the second output signal in response to a comparison between the pair of complementary triangle wave signals; a variable delay circuit coupled to receive the first and second output signals, the variable delay circuit outputting a delayed signal in response to a control signal; a clock buffer circuit coupled to receive and buffer the delayed circuit, the clock buffer circuit outputting an output signal of the DLL; and a phase detector coupled to the input reference signal and the output signal of the DLL, the phase comparator generating the control signal in response to a comparison between the input and output signals.
Claim 13
Dependent Claim
87 words
The DLL of claim 9, wherein the triangle wave generator comprises: a filter coupled across the complementary outputs; and a current switch coupled to receive the input reference signal, the current switch providing an output current having a direction of flow from one of the complementary outputs to the other of the complementary outputs, wherein the current switch reverses the direction of flow for the output current in response to the input reference signal, the filter integrating the output current to result in complementary triangle wave signals.
Claim 14
Dependent Claim
64 words
The DLL of claim 9, wherein the triangle wave generator comprises: a differential amplifier including a first input coupled to the input reference signal, a second input coupled to a complementary input reference signal, and the pair of complementary outputs; and a filter coupled across the complementary outputs, the filter causing the complementary outputs of the differential amplifier to output complementary triangle wave signals.
Claim 15
Dependent Claim
229 words
A phase shifting circuit comprising: (a) a current switch coupled to receive a pair of complementary input reference signals and including a pair of complementary outputs, the current switch for coupling to a power supply rail the current switch providing an output current having a direction of flow from one of the complementary outputs to the other of the complementary outputs, wherein the current switch reverses the direction of flow for the output current in response to the pair of complementary input reference signals; (b) a filter coupled across the complementary outputs and integrating the output current to generate a pair of complementary triangle wave signals, the filter comprising: (i) a first resistor having a first terminal coupled to one of the complementary outputs and a second terminal coupled to a common mode voltage; the common mode voltage being different than the power supply rail; (ii) a second resistor having a first terminal coupled to the other complementary output and a second terminal coupled to the common mode voltage; and (iii) capacitive means for providing a capacitance across the complementary outputs; and (c) a comparator having a pair of inputs coupled to receive the pair of complementary triangle wave signals, the comparator generating an output signal having a predetermined phase relationship with the input reference signal in response to a comparison between the pair of complementary triangle wave signals.
Claim 16
Dependent Claim
229 words
A phase shifting circuit comprising: (a) a current switch coupled to receive a pair of complementary input reference signals and including a pair of complementary outputs, the current switch for coupling to a power supply rail the current switch providing an output current having a direction of flow from one of the complementary outputs to the other of the complementary outputs, wherein the current switch reverses the direction of flow for the output current in response to the pair of complementary input reference signals; (b) a filter coupled across the complementary outputs and integrating the output current to generate a pair of complementary triangle wave signals, the filter comprising: (i) a first resistor having a first terminal coupled to one of the complementary outputs and a second terminal coupled to a common mode voltage; the common mode voltage being different than the power supply rail; (ii) a second resistor having a first terminal coupled to the other complementary output and a second terminal coupled to the common mode voltage; and (iii) capacitive means for providing a capacitance across the complementary outputs; and (c) a comparator having a pair of inputs coupled to receive the pair of complementary triangle wave signals, the comparator generating an output signal having a predetermined phase relationship with the input reference signal in response to a comparison between the pair of complementary triangle wave signals.
Claim 17
Dependent Claim
300 words
A quadrature clock generator for generating a first output signal and a second output signal that is approximately 90 degrees out of phase with the first output signal, the clock generator circuit comprising: (a) a first comparator having a pair of inputs coupled to a pair of complementary input reference signals, the first comparator generating the first output signal in response to the complementary input reference signals; (b) a phase shifting circuit coupled to the complementary input reference signals, the phase shifting circuit comprising: (i) a current switch coupled to receive the pair of complementary input reference signals and including a pair of complementary outputs, the current switch for coupling to a power supply rail the current switch providing an output current having a direction of flow from one of the complementary outputs to the other of the complementary outputs, wherein the current switch reverses the direction of flow for the output current in response to the pair of complementary input reference signals; (ii) a filter coupled across the complementary outputs and integrating the output current to generate a pair of complementary triangle wave signals, the filter comprising: (1) a first resistor having a first terminal coupled to one of the complementary outputs and a second terminal coupled to a common mode voltage; the common mode voltage being different than the power supply rail; (2) a second resistor having a first terminal coupled to the other complementary output and a second terminal coupled to the common mode voltage; and (3) capacitive means for providing a capacitance across the complementary outputs; and (iii) a second comparator having a pair of inputs coupled to receive the pair of complementary triangle wave signals, the comparator generating the second output signal in response to a comparison between the pair of complementary triangle wave signals.
Claim 18
Dependent Claim
300 words
A quadrature clock generator for generating a first output signal and a second output signal that is approximately 90 degrees out of phase with the first output signal, the clock generator circuit comprising: (a) a first comparator having a pair of inputs coupled to a pair of complementary input reference signals, the first comparator generating the first output signal in response to the complementary input reference signals; (b) a phase shifting circuit coupled to the complementary input reference signals, the phase shifting circuit comprising: (i) a current switch coupled to receive the pair of complementary input reference signals and including a pair of complementary outputs, the current switch for coupling to a power supply rail the current switch providing an output current having a direction of flow from one of the complementary outputs to the other of the complementary outputs, wherein the current switch reverses the direction of flow for the output current in response to the pair of complementary input reference signals; (ii) a filter coupled across the complementary outputs and integrating the output current to generate a pair of complementary triangle wave signals, the filter comprising: (1) a first resistor having a first terminal coupled to one of the complementary outputs and a second terminal coupled to a common mode voltage; the common mode voltage being different than the power supply rail; (2) a second resistor having a first terminal coupled to the other complementary output and a second terminal coupled to the common mode voltage; and (3) capacitive means for providing a capacitance across the complementary outputs; and (iii) a second comparator having a pair of inputs coupled to receive the pair of complementary triangle wave signals, the comparator generating the second output signal in response to a comparison between the pair of complementary triangle wave signals.
References Cited (Backward Citations)
US3296517A
Cited
US3546604A
Cited
US3555458A
Cited
US3921079A
Cited
US3911368A
Cited
US4021742A
Cited
US3965433A
Cited
US3982190A
Cited
US3997772A
Cited
US4110641A
Cited
US4285006A
Cited
US4156851A
Cited
US4151463A
Cited
JPS5535516A
Cited
EP0054323A2
Cited
US4789799A
Cited
EP0130384A1
Cited
US4607229A
Cited
US4719365A
Cited
US4635097A
Cited
US4623805A
Cited
US4721904A
Cited
US4644196A
Cited
US4739279A
Cited
US4724337A
Cited
JPS61228720A
Cited
US4638190A
Cited
US4746819A
Cited
US4806888A
Cited
US4908532A
Cited
DE3816973A1
Cited
US4813005A
Cited
US4745370A
Cited
US4935701A
Cited
US4878143A
Cited
US4866397A
Cited
EP0343899A2
Cited
US4870303A
Cited
US5015872A
Cited
US4992757A
Cited
US4994773A
Cited
EP0377897A2
Cited
US4893094A
Cited
US5123020A
Cited
EP0398751A2
Cited
DE4018615A1
Cited
US5111083A
Cited
US5164838A
Cited
JPH0410810A
Cited
US5220294A
Cited
GB2249442A
Cited
US5248946A
Cited
EP0490690A1
Cited
FR2670975A1
Cited
US5223755A
Cited
US5095233A
Cited
EP0521215A1
Cited
US5182476A
Cited
US5126693A
Cited
US5157276A
Cited
US5179303A
Cited
US5309162A
Cited
US5187448A
Cited
US5410263A
Cited
US5317288A
Cited
US5432480A
Cited
US5334953A
Cited
US5543742A
Cited
US5422529A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-09-14 | 2002-03-16 | 2002-09-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-09-14 | 2006-03-16 | 2006-09-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-09-14 | 2010-03-16 | 2010-09-15 | $7700.00 | Window Closed / Lapsed |