Patent US2679754A successfully refreshed from Google Patents.
US3921079A
Expired / Lapsed
US
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Multi-phase clock distribution system
Assignee: AG Communication Systems Corp
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Filing: 1974-05-13
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Granted: 1975-11-18
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Expires: 1994-05-13
Abstract
Abstract A multi-phase clock distribution system is provided for distributing M sets of N phase clock signals where each of the M sets is offset in phase relative to one another by a sub-multiple of the period of the driving signal frequency. Each clock phase output includes a state decoder counting circuit preceeded by a phase shift adjust circuit which provides an incremental phase shift whereby each of the M X N phase clock output signals can be individually adjusted in phase.
Inventors
- 👤 Samuel T Heffner
- 👤 Ronald F Kowalik
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 02:00
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/22; G11C7/222; G06; G06F; G06F1/00; G06F1/04; G06F1/10; H; H03; H03K; H03K5/00; H03K5/15; H03K5/15013; H03K5/1502
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
252 words
A multi-phase clock distribution circuit driven by a signal frequency source for generating N outputs, where N is an integer greater than one, each of said N outputs producing a pulse in a pulse train where each pulse in the pulse train is related to any other pulse by a multiple period of the source signal frequency, said clock distribution circuit comprising: phase shift adjust circuitry means (PAM) driven by said signal frequency for selectively delaying an edge of said signal waveform input, each of said N output chains including a PAM, each of said PAM being programmable to select the desired phase adjustment for each of said N outputs, said PAM including ramp generator circuitry means for generating a ramp voltage, reference voltage means for generating a reference voltage upon being programmed to select a specific reference voltage and comparator circuitry means for comparing said ramp voltage and said reference voltage for generating a pulse output, said pulse output continuing from the time said ramp voltage equals said reference voltage until the next successive edge of said signal frequency source occurs, and state decoder counting circuitry means (SDCM) driven by said PAM for generating an output, each of said PAM driving one of said SDCM, each SDCM having an output that is phase related to said other SDCM outputs by a multiple of the period of said source signal frequency and said selected delay in said PAM, each SDCM output reproducing the phase delay selected in said PAM driving said SDCM.
Claim 2
Dependent Claim
252 words
A multi-phase clock distribution circuit driven by a signal frequency source for generating N outputs, where N is an integer greater than one, each of said N outputs producing a pulse in a pulse train where each pulse in the pulse train is related to any other pulse by a multiple period of the source signal frequency, said clock distribution circuit comprising: phase shift adjust circuitry means (PAM) driven by said signal frequency for selectively delaying an edge of said signal waveform input, each of said N output chains including a PAM, each of said PAM being programmable to select the desired phase adjustment for each of said N outputs, said PAM including ramp generator circuitry means for generating a ramp voltage, reference voltage means for generating a reference voltage upon being programmed to select a specific reference voltage and comparator circuitry means for comparing said ramp voltage and said reference voltage for generating a pulse output, said pulse output continuing from the time said ramp voltage equals said reference voltage until the next successive edge of said signal frequency source occurs, and state decoder counting circuitry means (SDCM) driven by said PAM for generating an output, each of said PAM driving one of said SDCM, each SDCM having an output that is phase related to said other SDCM outputs by a multiple of the period of said source signal frequency and said selected delay in said PAM, each SDCM output reproducing the phase delay selected in said PAM driving said SDCM.
Claim 3
Dependent Claim
42 words
The clock distribution circuit as recited in claim 1 wherein each successive output of said N outputs is offset in pHase by one period of said source signal frequency from said preceeding output forming a pulse train on said N output lines.
Claim 4
Dependent Claim
18 words
The clock distribution circuit as recited in claim 2 wherein said SDCM includes a divide by N circuit.
Claim 5
Dependent Claim
50 words
The clock distribution circuit as recited in claim 1 wherein said reference voltage means includes a digital to analog converter that is digitally programmed, said digital programming inputs selecting a discrete reference voltage to be produced at the output of said reference voltage means and applied to said comparator means.
Claim 6
Dependent Claim
26 words
The clock distribution circuit as recited in claim 1 wherein said SDCM includes a synchronization input to control the output synchronization of said SDCM output pulses.
Claim 7
Dependent Claim
232 words
A multi-phase clock distribution circuit driven by a signal frequency source of frequency F for generating M phase related output pulse trains, where M is an integer greater than one, each of said M output pulse trains including N phase related outputs, said clock distribution circuit comprising: preliminary counting circuitry means for generating M phase related offset signal frequency outputs, each successive offset signal being offset in phase by 1/M periods of said source signal frequency from the next; phase shift adjust circuitry means (PAM) driven by said offset signal frequency outputs for selectively delaying an edge of said offset signal outputs, each of said N output chains of said M pulse train sets including a PAM, each of said PAM being programmable to select the desired phase adjustment for each of said N outputs of said M sets of pulse trains; and state decoder counting circuitry means (SDCM) driven by said PAM for generating an output of said N outputs in said M offset pulse train sets, each of said PAM driving an SDCM, each SDCM having an output that is phase related to said other SDCM outputs in each of said M phase related offset signal pulse trains by a multiple of the period of said offset signal frequency and said selected delay in said PAM, each SDCM output reproducing the phase delay selected in said PAM driving said SDCM.
Claim 8
Dependent Claim
232 words
A multi-phase clock distribution circuit driven by a signal frequency source of frequency F for generating M phase related output pulse trains, where M is an integer greater than one, each of said M output pulse trains including N phase related outputs, said clock distribution circuit comprising: preliminary counting circuitry means for generating M phase related offset signal frequency outputs, each successive offset signal being offset in phase by 1/M periods of said source signal frequency from the next; phase shift adjust circuitry means (PAM) driven by said offset signal frequency outputs for selectively delaying an edge of said offset signal outputs, each of said N output chains of said M pulse train sets including a PAM, each of said PAM being programmable to select the desired phase adjustment for each of said N outputs of said M sets of pulse trains; and state decoder counting circuitry means (SDCM) driven by said PAM for generating an output of said N outputs in said M offset pulse train sets, each of said PAM driving an SDCM, each SDCM having an output that is phase related to said other SDCM outputs in each of said M phase related offset signal pulse trains by a multiple of the period of said offset signal frequency and said selected delay in said PAM, each SDCM output reproducing the phase delay selected in said PAM driving said SDCM.
Claim 9
Dependent Claim
52 words
The clock distribution circuit as recited in claim 6 wherein each successive output of said N outputs in each of said M phase related output pulse trains is offset in phase by one period of said source signal frequency from said preceeding output forming a pulse train on said N output lines.
Claim 10
Dependent Claim
18 words
The clock distribution circuit as recited in claim 7 wherein said SDCM includes a divide by N circuit.
Claim 11
Dependent Claim
82 words
The clock distribution circuit as recited in claim 6 wherein said PAM includes ramp generator circuitry means for generating a ramp voltage, reference voltage means for generating a reference voltage upon being programmed to select a specific reference voltage and comparator circuitry means for comparing said ramp voltage and said reference voltage for generating a pulse output, said pulse output continuing from the time said ramp voltage equals said reference voltage until the next successive edge of said signal frequency source occurs.
Claim 12
Dependent Claim
50 words
The clock distribution circuit as recited in claim 9 wherein said reference voltage means includes a digital to analog converter that is digitally programmed, said digital programming inputs selecting a discrete reference voltage to be produced at the output of said reference voltage means and applied to said comparator means.
Claim 13
Dependent Claim
26 words
The clock distribution circuit as recited in claim 6 wherein said SDCM includes a synchronization input to control the output synchronization of said SDCM output pulses.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-11-17 | 1979-05-19 | 1979-11-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-11-17 | 1983-05-19 | 1983-11-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-11-17 | 1987-05-19 | 1987-11-18 | $7700.00 | Window Closed / Lapsed |