Processing techniques for achieving production-worthy, low dielectric, low dielectric, low interconnect resistance and high performance IC

Claim 1

A method for fabricating a semiconductor device formed on a wafer comprising source and drain regions contacted by source and drain contacts, respectively, and each source and drain region separated by a gate region contacted by a gate electrode, with a first level patterned interconnect contacting said source and drain contacts and said gate electrode in a desired pattern and with a second level patterned interconnect contacting said first level patterned interconnect by a plurality of metal lines, said metal lines separated by a first interlevel planarized dielectric material, comprising the steps of forming said second level patterned interconnect by: (a) forming and patterning a tri-layer resist on said first interlevel planarized dielectric layer to expose top portions of said metal lines, said tri-layer resist comprising a first layer of a dissolvable polymer, a second layer of a hard mask material, and a third layer of a resist material; (b) blanket-depositing on said wafer and said patterned tri-layer resist a low resistance metal layer having a resistance less than 2.8 μΩ-cm; (c) removing said first layer of said dissolvable polymer to thereby lift off metal from said low resistance metal layer thereover; and (d) spinning on a coating of a benzocyclobutene to directly cover said low resistance metal layer after said lift off, whereby said benzocyclobutene prevents diffusion of said low resistance metal layer.

Claim 2

A method for fabricating a semiconductor device formed on a wafer comprising source and drain regions contacted by source and drain contacts, respectively, and each source and drain region separated by a gate region contacted by a gate electrode, with a first level patterned interconnect contacting said source and drain contacts and said gate electrode in a desired pattern and with a second level patterned interconnect contacting said first level patterned interconnect by a plurality of metal lines, said metal lines separated by a first interlevel planarized dielectric material, comprising the steps of forming said second level patterned interconnect by: (a) forming and patterning a tri-layer resist on said first interlevel planarized dielectric layer to expose top portions of said metal lines, said tri-layer resist comprising a first layer of a dissolvable polymer, a second layer of a hard mask material, and a third layer of a resist material; (b) blanket-depositing on said wafer and said patterned tri-layer resist a low resistance metal layer having a resistance less than 2.8 μΩ-cm; (c) removing said first layer of said dissolvable polymer to thereby lift off metal from said low resistance metal layer thereover; and (d) spinning on a coating of a benzocyclobutene to directly cover said low resistance metal layer after said lift off, whereby said benzocyclobutene prevents diffusion of said low resistance metal layer.