US4219925A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of manufacturing a device in a silicon wafer
Assignee: AT&T Teletype Corp
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Filing: 1978-09-01
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Granted: 1980-09-02
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Expires: 1998-09-01
Abstract
Abstract A silicon body (10) of a first conductivity type is covered with a sandwich of silicon dioxide (12), polycrystalline silicon (14) and silicon nitride (16). Source, drain, and interconnect work sites of the body are exposed by a first photoshaping operation. The work sites are doped forming regions (21, 22, 23) of a second conductivity type. Silicon dioxide (24, 26, 28) is grown over the work sites. A second photoshaping operation provides an opening 36. The walls of the opening 36 on two opposite sides comprise sides of the sandwich layer as established by the first photoshaping operation and the two remaining walls comprise sides of the silicon dioxide as established by the second photoshaping operation. Silicon nitride (44) is next deposited over the entire wafer (15) which is then photoshaped to define the field regions (46, 48). The etching process is continued to remove part of the silicon body as well as the sides of those exposed regions. Thereafter, silicon dioxide (47, 49) is grown in the field regions. The remaining silicon nitride layer is removed to reveal the underlying conductive polycrystalline silicon (14) at the gate region, the walls of the contact opening 36 and the interconnect region 23. A conductive material (51, 50) is deposited over the wafer (15) and then photoshaped to provide the desired pattern of ohmic interconnections.
Inventors
- 👤 Richard H. Heeren
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 15:48
CPC Classifications
H; H10; H10P; H10P76/00; H10P76/40; H10D; H10D30/00; H10D30/60; Y; Y10; Y10S; Y10S148/00; Y10S148/053; Y10S148/114; Y10S148/141
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
336 words
A method of manufacturing a device in a silicon wafer (15) of a first conductivity type having formed thereon a masking medium (11) having an oxygen impervious exposed surface, masking and removing selected portions of the masking medium to expose the surface of the wafer to define at least one pair of spaced apart work sites (17, 18, 19), each of the work sites being doped to form regions (21, 22, 23) of a second conductivity type, and placing an oxide layer (24, 26, 28) over the altered regions and over any other exposed surface capable of being oxidized, characterized by: 1--masking the surface of the wafer to define an electrical contact area over a selected portion of at least one of said second conductivity type regions; 2--removing that portion of the oxide in the defined area thus producing an opening (36) to the underlying doped region (23) whereby at least one wall of the opening is defined by an edge of said masking medium as previously defined by said first mentioned masking step and any remaining wall of the opening is defined by the oxide (28) formed over the doped region (23) as defined by said second mentioned masking step; 3--covering the entire exposed surface of the wafer with an oxygen impervious masking layer (44); 4--removing selected portions of the masking medium (11) and of the oxygen impervious masking layer (44) while retaining that portion of the masking layer (44) overlaying the doped region (23) defined by said opening, to define field regions (46, 48) whereat the wafer (15) is to be covered with a field oxide (49, 53); 5--forming a field oxide (49, 53) over the field regions of the wafer (15); 6--removing the remaining oxygen impervious surface regions (45, 52); 7--forming a conductor over the entire surface of the wafer; and 8--removing the conductor from all undesired portions of the surface to form a desired pattern of electrical interconnection which at least overlays a portion of the doped region defined by said opening.
Claim 2
Independent Claim
336 words
A method of manufacturing a device in a silicon wafer (15) of a first conductivity type having formed thereon a masking medium (11) having an oxygen impervious exposed surface, masking and removing selected portions of the masking medium to expose the surface of the wafer to define at least one pair of spaced apart work sites (17, 18, 19), each of the work sites being doped to form regions (21, 22, 23) of a second conductivity type, and placing an oxide layer (24, 26, 28) over the altered regions and over any other exposed surface capable of being oxidized, characterized by: 1--masking the surface of the wafer to define an electrical contact area over a selected portion of at least one of said second conductivity type regions; 2--removing that portion of the oxide in the defined area thus producing an opening (36) to the underlying doped region (23) whereby at least one wall of the opening is defined by an edge of said masking medium as previously defined by said first mentioned masking step and any remaining wall of the opening is defined by the oxide (28) formed over the doped region (23) as defined by said second mentioned masking step; 3--covering the entire exposed surface of the wafer with an oxygen impervious masking layer (44); 4--removing selected portions of the masking medium (11) and of the oxygen impervious masking layer (44) while retaining that portion of the masking layer (44) overlaying the doped region (23) defined by said opening, to define field regions (46, 48) whereat the wafer (15) is to be covered with a field oxide (49, 53); 5--forming a field oxide (49, 53) over the field regions of the wafer (15); 6--removing the remaining oxygen impervious surface regions (45, 52); 7--forming a conductor over the entire surface of the wafer; and 8--removing the conductor from all undesired portions of the surface to form a desired pattern of electrical interconnection which at least overlays a portion of the doped region defined by said opening.
Claim 3
Dependent Claim
37 words
The method of claim 1 which further includes the step of removing a portion of the body of the wafer 15 and portions of any adjacent doped regions (21, 22) after step 4 and before step 5.
Claim 4
Dependent Claim
59 words
The method of claim 1 wherein said masking medium (11) over the surface of the wafer comprises a sandwich including a layer (12) of silicon dioxide placed adjacent the surface of the wafer, a layer (14) of polycrystalline silicon material over the surface of the silicon dioxide layer, and an exposed oxygen impervious layer (16) of silicon nitride (16).
Claim 5
Dependent Claim
52 words
The method of claim 3 where in step 6 only the silicon nitride layer (16) of said masking medium (11) is removed and at least one of the conductors (51) formed in step 8 is formed in contact with the layer (14) of polycrystalline silicon over the gate area of the transistor.
Claim 6
Dependent Claim
29 words
The method of claim 4 which further includes the step of treating the polycrystalline silicon material (14) exposed in the gate area with a dopant to render it conductive.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-09-02 | 1984-03-03 | 1984-09-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-09-02 | 1988-03-03 | 1988-09-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-09-02 | 1992-03-03 | 1992-09-02 | $7700.00 | Window Closed / Lapsed |