US5657206A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Conductive epoxy flip-chip package and method
Assignee: VERTICAL CIRCUITS SOLUTIONS Inc
•
Filing: 1995-01-19
•
Granted: 1997-08-12
•
Expires: 2015-01-19
Abstract
Abstract A method and apparatus for producing a multichip package comprising semiconductor chip and a substrate. The semiconductor chip includes conventional inner bond pads that are rerouted to other areas on the chip to facilitate connection with the substrate. The inner bonds are rerouted by covering the chip with a first insulation layer and opening the first insulation layer over the inner bond pads. A metal layer is then disposed over the first insulation layer in contact with the inner bond pads. A second insulation layer is disposed over the metal layer, and the second insulation layer is opened to expose selected portions of the metal layer to form external connection points. Electrically conductive epoxy is then disposed between the external connection points of the semiconductor chip and the terminals of the substrate, thereby electrically connecting the semiconductor chip to the substrate.
Inventors
- 👤 David V. Pedersen
- 👤 Michael G. Finley
- 👤 Kenneth M. Sautter
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 17:33
CPC Classifications
H; H01; H01R; H01R29/00; H01R4/00; H01R4/04; H05; H05K; H05K3/00; H05K3/30; H05K3/303; H05K3/305; H05K3/32; H05K3/321; H05K7/00; H05K7/02; H05K7/023; H10; H10D; H10D62/00; H10D62/10; H10D62/117; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/44; H10W20/4473; H10W20/482; H10W20/484; H10W20/49; H10W20/493; H10W40/00; H10W40/20; H10W40/25; H10W40/251; H10W70/00; H10W70/60; H10W70/611; H10W70/62; H10W70/641; H10W72/00; H10W72/20; H10W90/00; H10W90/401; H05K2201/00; H05K2201/09; H05K2201/09209; H05K2201/09372; H05K2201/09472; H05K2201/10; H05K2201/10431; H05K2201/10439; H05K2201/10477; H05K2201/10613; H05K2201/10621; H05K2201/10674; H05K2201/10719; H05K2201/10727; H10W46/00; H10W72/01; H10W72/071; H10W72/0711; H10W72/07141; H10W72/072; H10W72/07231; H10W72/07236; H10W72/073; H10W72/07331; H10W72/251; H10W72/30; H10W72/321; H10W72/325; H10W72/351; H10W72/353; H10W72/354; H10W72/834; H10W74/00; H10W90/20; H10W90/284; H10W90/701; H10W90/721; H10W90/722; H10W90/731; H10W90/732; H10W90/751; H10W90/754; Y; Y02; Y02P; Y02P70/00; Y02P70/50; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49124; Y10T29/49126; Y10T29/4913; Y10T29/49146; Y10T29/49169; Y10T29/49171
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
154 words
A semiconductor chip package, comprising: a substrate having a plurality of terminals; a semiconductor chip on said substrate, said semiconductor chip including, a plurality of inner bond pads, a first insulation layer covering said chip, a first plurality of holes in said first insulation layer exposing said inner bond pads, a metal layer disposed over said first insulation layer to form an electrical contact with said inner bond pads, a second insulation layer disposed over said metal layer, and a second plurality of holes in said second insulation layer exposing selected portions of said metal layer to form external connection points; electrically conductive epoxy disposed between said external connection points of said semiconductor chip and said terminals of said substrate, thereby electrically connecting said semiconductor chip to said substrate, and glass sphere means disposed between said external connection points and said terminals for maintaining a minimum bond thickness between said chip and said substrate.
Claim 2
Dependent Claim
154 words
A semiconductor chip package, comprising: a substrate having a plurality of terminals; a semiconductor chip on said substrate, said semiconductor chip including, a plurality of inner bond pads, a first insulation layer covering said chip, a first plurality of holes in said first insulation layer exposing said inner bond pads, a metal layer disposed over said first insulation layer to form an electrical contact with said inner bond pads, a second insulation layer disposed over said metal layer, and a second plurality of holes in said second insulation layer exposing selected portions of said metal layer to form external connection points; electrically conductive epoxy disposed between said external connection points of said semiconductor chip and said terminals of said substrate, thereby electrically connecting said semiconductor chip to said substrate, and glass sphere means disposed between said external connection points and said terminals for maintaining a minimum bond thickness between said chip and said substrate.
Claim 3
Dependent Claim
16 words
A semiconductor chip package as in claim 1, wherein said substrate is a printed circuit board.
Claim 4
Dependent Claim
30 words
A semiconductor chip package as in claim 2, wherein said semiconductor chip includes four edges and said external contact points are located on said semiconductor chip internally from said edges.
Claim 5
Dependent Claim
33 words
A semiconductor chip package as in claim 1, wherein said semiconductor chip is disposed on said substrate face-down such that said external connection points are positioned directly above said terminals on said substrate.
Claim 6
Dependent Claim
31 words
A semiconductor chip package as in claim 1, wherein said semiconductor chip is disposed on said substrate face-up such that said external connection points face-away from said terminals on said substrate.
Claim 7
Dependent Claim
29 words
A semiconductor chip package as in claim 5, wherein said semiconductor chip includes four edges and said external contact points are located along the edges of said semiconductor chip.
Claim 8
Dependent Claim
39 words
A semiconductor chip package as in claim 6, wherein said semiconductor chip includes beveled edge walls and said electrically conductive epoxy extends down from said external contact points along said beveled edge walls to said terminals on said substrate.
Claim 9
Independent Claim
148 words
A method for producing a multichip package, said method comprising the steps of: providing inner bond pads on said chip; covering said chip with a first insulation layer; forming a first plurality of holes in said first insulation layer to expose said inner bond pads; disposing a metal layer over said first insulation layer such that said metal layer is in electrical contact with said inner bond pads; disposing a second insulation layer over said metal layer; exposing selected portions of said metal layer to form external connection points; providing a substrate having a plurality of terminals; disposing conductive epoxy between said external connection points of said chip and said terminals of said substrate to electrically connect said chip to said substrate, and providing glass sphere means disposed between said external connection points and said terminals for maintaining a minimum bond thickness between said chip and said substrate.
Claim 10
Independent Claim
148 words
A method for producing a multichip package, said method comprising the steps of: providing inner bond pads on said chip; covering said chip with a first insulation layer; forming a first plurality of holes in said first insulation layer to expose said inner bond pads; disposing a metal layer over said first insulation layer such that said metal layer is in electrical contact with said inner bond pads; disposing a second insulation layer over said metal layer; exposing selected portions of said metal layer to form external connection points; providing a substrate having a plurality of terminals; disposing conductive epoxy between said external connection points of said chip and said terminals of said substrate to electrically connect said chip to said substrate, and providing glass sphere means disposed between said external connection points and said terminals for maintaining a minimum bond thickness between said chip and said substrate.
Claim 11
Dependent Claim
34 words
A method as in claim 8, further comprising the step of disposing said chip is on said substrate face-down such that said external connection points are positioned directly above said terminals on said substrate.
Claim 12
Dependent Claim
30 words
A method as in claim 9, further comprising the steps of: providing said chip with four edges; and forming said external contact points on said chip internally from said edges.
Claim 13
Dependent Claim
31 words
A method as in claim 8, further comprising the step of disposing said chip face-up on said substrate such that said external connection points face-away from said terminals on said substrate.
Claim 14
Dependent Claim
29 words
A method as in claim 11, further comprising the steps of: providing said chip with four edges; and forming said external contact points along the edges of said chip.
Claim 15
Dependent Claim
40 words
A method as in claim 12, further comprising the steps of: providing said chip with beveled edge walls; and dispensing said electrically conductive epoxy from said external contact points along said beveled edge walls to said terminals on said substrate.
Claim 16
Dependent Claim
189 words
A flip-chip package, comprising: a printed circuit board having a plurality of terminals; a flip-chip including, four edges; a plurality of inner bond pads, a first insulation layer covering said flip-chip, a first plurality of holes in said first insulation layer exposing said inner bond pads, a metal layer disposed over said first insulation layer in electrical contact with said inner bond pads a second insulation layer disposed over said metal layer, and a second plurality of holes in said second insulation layer exposing selected portions of said metal layer to form external connection points, said external connection points being located on said flip-chip internally from said edges; said flip-chip disposed on said printed circuit board face-down such that said external connection points are positioned directly above said terminals on said printed circuit board; electrically conductive epoxy disposed between said external connection points of said flip-chip and said terminals of said printed circuit board, thereby electrically connecting said chip to said printed circuit board, and glass sphere means disposed between said external connection points and said terminals for maintaining a minimum bond thickness between said chip and said substrate.
Claim 17
Dependent Claim
189 words
A flip-chip package, comprising: a printed circuit board having a plurality of terminals; a flip-chip including, four edges; a plurality of inner bond pads, a first insulation layer covering said flip-chip, a first plurality of holes in said first insulation layer exposing said inner bond pads, a metal layer disposed over said first insulation layer in electrical contact with said inner bond pads a second insulation layer disposed over said metal layer, and a second plurality of holes in said second insulation layer exposing selected portions of said metal layer to form external connection points, said external connection points being located on said flip-chip internally from said edges; said flip-chip disposed on said printed circuit board face-down such that said external connection points are positioned directly above said terminals on said printed circuit board; electrically conductive epoxy disposed between said external connection points of said flip-chip and said terminals of said printed circuit board, thereby electrically connecting said chip to said printed circuit board, and glass sphere means disposed between said external connection points and said terminals for maintaining a minimum bond thickness between said chip and said substrate.
Claim 18
Dependent Claim
196 words
A chip package, comprising: a printed circuit board having a plurality of terminals; a chip including, four edges; a plurality of inner bond pads, a first insulation layer covering said chip, a first plurality of holes in said first insulation layer exposing said inner bond pads, a metal layer disposed over said first insulation layer in electrical contact with said inner bond pads a second insulation layer disposed over said metal layer, a second plurality of holes in said second insulation layer exposing selected portions of said metal layer to form external connection points, said external connection points being located along said edges of said chip, and beveled edge walls located at the outer edges of said chip and sloping toward the center of said chip; said chip disposed on said printed circuit board face-up; and electrically conductive epoxy disposed along said beveled edge walls between said external contact points of said chip and said terminals of said printed circuit board, thereby electrically connecting said chip to said printed circuit board, and glass sphere means disposed between said external contact points and said terminals for maintaining a minimum bond thickness between said chip and said substrate.
Claim 19
Dependent Claim
196 words
A chip package, comprising: a printed circuit board having a plurality of terminals; a chip including, four edges; a plurality of inner bond pads, a first insulation layer covering said chip, a first plurality of holes in said first insulation layer exposing said inner bond pads, a metal layer disposed over said first insulation layer in electrical contact with said inner bond pads a second insulation layer disposed over said metal layer, a second plurality of holes in said second insulation layer exposing selected portions of said metal layer to form external connection points, said external connection points being located along said edges of said chip, and beveled edge walls located at the outer edges of said chip and sloping toward the center of said chip; said chip disposed on said printed circuit board face-up; and electrically conductive epoxy disposed along said beveled edge walls between said external contact points of said chip and said terminals of said printed circuit board, thereby electrically connecting said chip to said printed circuit board, and glass sphere means disposed between said external contact points and said terminals for maintaining a minimum bond thickness between said chip and said substrate.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-08-11 | 2001-02-10 | 2001-08-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-08-11 | 2005-02-10 | 2005-08-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-08-11 | 2009-02-10 | 2009-08-12 | $7700.00 | Window Closed / Lapsed |