US5055425A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Stacked solid via formation in integrated circuit systems
Assignee: HP Inc
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Filing: 1989-06-01
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Granted: 1991-10-08
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Expires: 2009-06-01
Abstract
Abstract A method of forming solid copper vias in a dielectric layer permits stacked up vias in a multi-layer multi-chip carrier. An conducting layer is deposited over a substrate and lines of a first interconnect layer formed on the substrate. An aperture formed in a photoresist layer over said lines is filled with copper by electroplating to form a solid via. The via can be polished until its top is flat. Using a photoresist mask, the conductive layer used for electroplating is removed between the lines. A dielectric layer is then formed over the lines and via. A bulge in the dielectric over the via is removed by etching through an aperture defined in a photoresist layer, which is then stripped. A second interconnect layer can be formed on the resulting structure. The foregoing steps can be iterated to build a multi-layer structure with stacked up vias.
Inventors
- 👤 Jacques Leibovitz
- 👤 Maria L. Cobarruviaz
- 👤 Kenneth D. Scholz
- 👤 Clinton C. Chao
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 07:56
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/42; H05; H05K; H05K3/00; H05K3/40; H05K3/42; H05K3/421; H05K3/46; H05K3/4644; H05K3/4647; H05K2201/00; H05K2201/01; H05K2201/0137; H05K2201/0154; H05K2201/09; H05K2201/09209; H05K2201/095; H05K2201/09563; H05K2203/00; H05K2203/05; H05K2203/0502; H05K2203/0542; H05K2203/07; H05K2203/0703; H05K2203/0733; H05K3/0011; H05K3/0017; H05K3/0041; H05K3/22; H05K3/24; H05K3/243; H05K3/38; H05K3/388; H05K3/423; H05K3/425; H05K3/426; H05K3/467; Y; Y10; Y10S; Y10S148/00; Y10S148/164; Y10S438/00; Y10S438/959
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
101 words
A method of forming an integrated circuit structure including solid vias, said method comprising the steps of: a) forming a circuit pattern on a substrate; b) depositing a photoresist layer on the circuit pattern, and forming apertures in said photoresist layer; c) plating solid metal vias in the apertures and, then, removing said photoresist layer; d) depositing a first dielectric layer over the circuit pattern and the solid metal vias; e) defining apertures in the first dielectric layer over the solid metal vias; and f) etching the apertures in the first dielectric layer to expose surfaces of the solid metal vias.
Claim 2
Independent Claim
101 words
A method of forming an integrated circuit structure including solid vias, said method comprising the steps of: a) forming a circuit pattern on a substrate; b) depositing a photoresist layer on the circuit pattern, and forming apertures in said photoresist layer; c) plating solid metal vias in the apertures and, then, removing said photoresist layer; d) depositing a first dielectric layer over the circuit pattern and the solid metal vias; e) defining apertures in the first dielectric layer over the solid metal vias; and f) etching the apertures in the first dielectric layer to expose surfaces of the solid metal vias.
Claim 3
Dependent Claim
30 words
The method of claim 1 wherein step b further includes depositing an electrically conductive layer over the circuit pattern and said substrate prior to the deposition of said photoresist layer.
Claim 4
Dependent Claim
19 words
The method of claim 2 wherein said electrically conductive layer comprises a copper layer sandwiched between metal adhesive layers.
Claim 5
Dependent Claim
55 words
The method of claim 3 further comprising the steps of forming a second circuit pattern, including second circuit layer lines and second circuit layer vias, on the structure resulting from step f with some of the vias in the second circuit layer vias being stacked on some of the vias in the first dielectric layer.
Claim 6
Dependent Claim
23 words
The method of claim 4 further comprising repeating steps b through f to form a second dielectric layer over said second circuit pattern.
Claim 7
Dependent Claim
39 words
The method of claim 5 wherein selected ones of the solid metal vias in the second dielectric layer are interconnected with selected ones of the solid metal vias in the first circuit layer to form a multiple layer interconnect.
Claim 8
Dependent Claim
18 words
The method of claim 2 wherein the plating step comprises electroplating the vias on the first dielectric layer.
Claim 9
Dependent Claim
23 words
The method of claim 7 wherein the depositing step comprises removing portions of the electrically conductive layer prior to depositing the dielectric layer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-10-07 | 1995-04-08 | 1995-10-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-10-07 | 1999-04-08 | 1999-10-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-10-07 | 2003-04-08 | 2003-10-08 | $7700.00 | Window Closed / Lapsed |