US4879257A
Expired / Lapsed
US
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Planarization process
Assignee: LSI Corp
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Filing: 1987-11-18
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Granted: 1989-11-07
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Expires: 2007-11-18
Abstract
Abstract A method for forming a multilayer integrated circuit is described wherein the resultant top surface thereof is substantially planar. The method involves first forming a layer of connecting metallization on integrated circuit components formed in a conventional manner. Then a first layer of dielectric is formed on the metallization layer. Next a second dielectric layer is formed on the first dielectric layer. Via areas are then formed by etching the first and second dielectric layers in order to expose selected areas of the first metallization layer, and filled with metal to form vias. A layer of photoresist is deposited on all surfaces. Lastly, the surface is etched using an etchant that etches dielectric, metal and photoresist at substantially the same rate such that said vias are exposed and a planar top surface produced.
Inventors
- 👤 Roger Patrick
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 07:32
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/092; Y; Y10; Y10S; Y10S148/00; Y10S148/051; Y10S148/081; Y10S148/131
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
208 words
A method for manufacturing a multilayer integrated circuit comprising: (a) forming a plurality of components on an integrated circuit substrate to form a first component layer; (b) forming a first layer of interconnecting metallization over said components; (c) depositing a first layer of dielectric material over said first metallization layer; (d) depositing a second layer of dielectric material over said first layer of dielectric material; (e) masking said second dielectric layer wherein said mask permits etching in those areas where a contact with said first layer of interconnecting metallization is desired; (f) etching to form cavities through said first and second dielectric layers wherein said cavities expose said first layer of interconnecting metallization in those areas where contact with said first layer of interconnecting metallization is desired; (g) filling said cavities with metal to form metal filled cavities; (h) depositing a layer of photoresist over said second dielectric layer and said metal filled cavities; and (i) etching the integrated circuit with a chemistry which etches dielectric, metal and photoresist at substantially the same rate wherein said etching removes said photoresist and portions of said dielectric and metal filled cavities to expose said metal filled cavities and produce a top surface on said integrated circuit which is substantially planar.
Claim 2
Independent Claim
208 words
A method for manufacturing a multilayer integrated circuit comprising: (a) forming a plurality of components on an integrated circuit substrate to form a first component layer; (b) forming a first layer of interconnecting metallization over said components; (c) depositing a first layer of dielectric material over said first metallization layer; (d) depositing a second layer of dielectric material over said first layer of dielectric material; (e) masking said second dielectric layer wherein said mask permits etching in those areas where a contact with said first layer of interconnecting metallization is desired; (f) etching to form cavities through said first and second dielectric layers wherein said cavities expose said first layer of interconnecting metallization in those areas where contact with said first layer of interconnecting metallization is desired; (g) filling said cavities with metal to form metal filled cavities; (h) depositing a layer of photoresist over said second dielectric layer and said metal filled cavities; and (i) etching the integrated circuit with a chemistry which etches dielectric, metal and photoresist at substantially the same rate wherein said etching removes said photoresist and portions of said dielectric and metal filled cavities to expose said metal filled cavities and produce a top surface on said integrated circuit which is substantially planar.
Claim 3
Dependent Claim
33 words
The method of claim 1 further including the steps of depositing a second interconnecting metallization layer on said planar surface wherein said second metallization layer contacts said metal filled cavities in selected areas.
Claim 4
Dependent Claim
35 words
The method of claim 1 further including the steps of depositing a second component layer on said planar surface wherein the component of said second component layer contact said metal filled cavities in selected areas.
Claim 5
Dependent Claim
15 words
The method of claim 1 wherein the metal used to fill said cavities is tungsten.
Claim 6
Dependent Claim
13 words
The method of claim 1 wherein said first dielectric layer is silicon dioxide.
Claim 7
Dependent Claim
13 words
The method of claim 1 wherein said second dielectric layer is silicon nitride.
Claim 8
Dependent Claim
15 words
The method of claim 1 wherein the metal used to fill said cavities is aluminum.
Claim 9
Dependent Claim
29 words
The method of claim 1 wherein said step of filling said cavities includes the step of filling said cavities by the selective low pressure chemical vapor deposition of tungsten.
Claim 10
Dependent Claim
25 words
The method of claim 1 wherein said step of filling said cavities includes the step of filling said cavities by the non-selective deposition of aluminum.
Claim 11
Dependent Claim
12 words
The method of claim 9 wherein said aluminum is deposited by sputtering.
Claim 12
Independent Claim
242 words
A method for manufacturing a multilayer integrated circuit comprising: (a) forming a plurality of components on an integrated circuit substrate to form a first component layer; (b) forming a layer of interconnecting metallization over said components; (c) depositing a first layer of dielectric material over said metallization layer; (d) depositing a second layer of dielectric material over said first layer of dielectric material; (e) masking said second dielectric layer wherein said mask permits etching in those areas where a contact with said first layer of interconnecting metallization is desired; (f) etching to produce cavities through said first and second dielectric layers wherein said cavities expose said first layer of interconnecting metallization in those areas where contact with said first layer of interconnecting metallization is desired; (g) filling said cavities with metal to form metal filled cavities; (h) depositing a layer of photoresist over said second dielectric layer and said metal filled cavities; (i) etching the integrated circuit with a chemistry which etches dielectric, metal and photoresist at substantially the same rate wherein said etching removes said photoresist and portions of said dielectric and metal filled cavities to expose said metal filled cavities and produce a top surface on said integrated circuit which is substantially planar; (j) depositing another interconnecting metallization layer on said planar surface wherein said metallization layer contacts said metal filled cavities in selected areas; and (k) Repeating steps (c) through (j) to form additional layers of interconnecting metallization patterns.
Claim 13
Independent Claim
242 words
A method for manufacturing a multilayer integrated circuit comprising: (a) forming a plurality of components on an integrated circuit substrate to form a first component layer; (b) forming a layer of interconnecting metallization over said components; (c) depositing a first layer of dielectric material over said metallization layer; (d) depositing a second layer of dielectric material over said first layer of dielectric material; (e) masking said second dielectric layer wherein said mask permits etching in those areas where a contact with said first layer of interconnecting metallization is desired; (f) etching to produce cavities through said first and second dielectric layers wherein said cavities expose said first layer of interconnecting metallization in those areas where contact with said first layer of interconnecting metallization is desired; (g) filling said cavities with metal to form metal filled cavities; (h) depositing a layer of photoresist over said second dielectric layer and said metal filled cavities; (i) etching the integrated circuit with a chemistry which etches dielectric, metal and photoresist at substantially the same rate wherein said etching removes said photoresist and portions of said dielectric and metal filled cavities to expose said metal filled cavities and produce a top surface on said integrated circuit which is substantially planar; (j) depositing another interconnecting metallization layer on said planar surface wherein said metallization layer contacts said metal filled cavities in selected areas; and (k) Repeating steps (c) through (j) to form additional layers of interconnecting metallization patterns.
Claim 14
Independent Claim
237 words
A method for manufacturing a multilayer integrated circuit comprising: (a) forming a plurality of components on an integrated circuit substrate to form a first component layer; (b) forming a layer of interconnecting metallization over said components; (c) depositing a first layer of dielectric material over said metallization layer; (d) depositing a second layer of dielectric material over said first layer of dielectric material; (e) masking said second dielectric layer wherein said mask permits etching in those areas where a contact with said first layer of interconnecting metallization is desired; (f) etching to produce cavities through said first and second dielectric layers wherein said cavities expose said first layer of interconnecting metallization in those areas where contact with said first layer of interconnecting metallization is desired; (g) filling said cavities with metal to form metal filled cavities; (h) depositing a layer of photoresist over said second dielectric layer and said metal filled cavities; (i) etching the integrated circuit with a chemistry which etches dielectric, metal and photoresist at substantially the same rate wherein said etching removes said photoresist and portions of said dielectric and metal filled cavities to expose said metal filled cavities and produce a top surface on said integrated circuit which is substantially planar; (j) forming another device layer on said planar surface wherein said device layer contacts said metal filled cavities inselected areas; and (k) repeating steps (c) through (j) to form additional device layers.
Claim 15
Independent Claim
237 words
A method for manufacturing a multilayer integrated circuit comprising: (a) forming a plurality of components on an integrated circuit substrate to form a first component layer; (b) forming a layer of interconnecting metallization over said components; (c) depositing a first layer of dielectric material over said metallization layer; (d) depositing a second layer of dielectric material over said first layer of dielectric material; (e) masking said second dielectric layer wherein said mask permits etching in those areas where a contact with said first layer of interconnecting metallization is desired; (f) etching to produce cavities through said first and second dielectric layers wherein said cavities expose said first layer of interconnecting metallization in those areas where contact with said first layer of interconnecting metallization is desired; (g) filling said cavities with metal to form metal filled cavities; (h) depositing a layer of photoresist over said second dielectric layer and said metal filled cavities; (i) etching the integrated circuit with a chemistry which etches dielectric, metal and photoresist at substantially the same rate wherein said etching removes said photoresist and portions of said dielectric and metal filled cavities to expose said metal filled cavities and produce a top surface on said integrated circuit which is substantially planar; (j) forming another device layer on said planar surface wherein said device layer contacts said metal filled cavities inselected areas; and (k) repeating steps (c) through (j) to form additional device layers.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-11-06 | 1993-05-08 | 1993-11-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-11-06 | 1997-05-08 | 1997-11-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-11-06 | 2001-05-08 | 2001-11-07 | $7700.00 | Window Closed / Lapsed |