Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
244 words
A method for forming an insulating layer on a surface of a semiconductor device, comprising: (a) providing, on the device surface, a first patterned feature of thickness X 1 and a second patterned feature of thickness X 2 , wherein X 2 >X 1 ; (b) forming a topographically conformal insulating layer of thickness T 3 over the patterned features and the surface, wherein T 3 >X 2 ; (c) applying a flowable layer over the insulating layer; (d) flowing the flowable layer so as to yield a substantially planar surface; (e) substantially uniformly thinning the flowable layer until that portion of the insulating layer that overlies the second feature is exposed; (f) simultaneously thinning the flowable layer and the exposed surface of the insulating layer that overlies the second feature so as to remove the flowable layer at a greater rate than the insulating layer; (g) stopping said simultaneous thinning when that portion of the insulating layer that overlies the first feature is exposed; and (h) thinning the exposed insulating layer to a thickness D 1 over the first feature and a thickness D 2 over the second feature without reducing the thickness T 3 over said surface, such that the non-uniformity of insulating layer thickness |D 1 -D 2 | is within a first predetermined range and the maximum step heights |(D 1 +X 1 )-T 3 | and |(D 2 +X 2 )-T 3 | are within a second predetermined range.
Claim 2
Independent Claim
244 words
A method for forming an insulating layer on a surface of a semiconductor device, comprising: (a) providing, on the device surface, a first patterned feature of thickness X 1 and a second patterned feature of thickness X 2 , wherein X 2 >X 1 ; (b) forming a topographically conformal insulating layer of thickness T 3 over the patterned features and the surface, wherein T 3 >X 2 ; (c) applying a flowable layer over the insulating layer; (d) flowing the flowable layer so as to yield a substantially planar surface; (e) substantially uniformly thinning the flowable layer until that portion of the insulating layer that overlies the second feature is exposed; (f) simultaneously thinning the flowable layer and the exposed surface of the insulating layer that overlies the second feature so as to remove the flowable layer at a greater rate than the insulating layer; (g) stopping said simultaneous thinning when that portion of the insulating layer that overlies the first feature is exposed; and (h) thinning the exposed insulating layer to a thickness D 1 over the first feature and a thickness D 2 over the second feature without reducing the thickness T 3 over said surface, such that the non-uniformity of insulating layer thickness |D 1 -D 2 | is within a first predetermined range and the maximum step heights |(D 1 +X 1 )-T 3 | and |(D 2 +X 2 )-T 3 | are within a second predetermined range.
Claim 3
Dependent Claim
27 words
A method in accordance with claim 1 wherein said first predetermined range is 0 to 3000 Angstroms and said second predetermined range is 0 to 5000 Angstroms.
Claim 4
Dependent Claim
16 words
A method in accordance with claim 1 wherein T 3 is approximately twice D 2 .
Claim 5
Dependent Claim
14 words
A method in accordance with claim 1 wherein said insulating layer is silicon dioxide.
Claim 6
Dependent Claim
13 words
A method in accordance with claim 1 wherein said flowable layer is photoresist.
Claim 7
Dependent Claim
29 words
A method in accordance with claim 1 wherein X 1 ≅7500 Å, X 2 ≅10,000 Å, T 3 ≅15,000 Å, D 1 ≅9000 Å and D 2 ≅7000 Å.
Claim 8
Dependent Claim
23 words
A method in accordance with claim 1 wherein all of said thinning steps are performed in situ in a plasma reactive ion etcher.
Claim 9
Dependent Claim
17 words
A method in accordance with claim 1 wherein said first and second patterned features comprise conductor lines.
Claim 10
Dependent Claim
26 words
A method in accordance with claim 8 wherein said first patterned features comprises polycrystalline silicon and said second patterned feature comprises metal disposed on polycrystalline silicon.