US4721689A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for simultaneously forming an interconnection level and via studs
Assignee: International Business Machines Corp
•
Filing: 1986-08-28
•
Granted: 1988-01-26
•
Expires: 2006-08-28
Abstract
Abstract A method for simultaneously forming a level of interconnection metallurgy over, and inter-level via studs through, an insulating layer of a semiconductor chip. The method comprises the steps of forming a plurality of via holes in the insulating layer, high-mobility sputtering conductive material on to the surface of the insulating layer and into the via holes therein, masking the conductive material layer, and then ion beam milling through the mask to form a patterned interconnection layer. The high-mobility sputtering step is accomplished by reducing the background pressure to below 10 -7 Torr to eliminate non-mobile species, maintaining a sputter pressure of less than 7 microns, maintaining an appropriate chip bias level to keep the conductive material molecules mobile until they reach their lowest energy state, and maintaining the temperature of the chip at a level so that a high sputter species mobility is maintained. This high-mobility sputtering forms a substantially planar conductive layer and fills the via holes without void formation. The foregoing process permits extremely dense interconnection levels, is especially suited for multiple interconnection level designs, and is extendable to large diameter wafer fabrication.
Inventors
- 👤 Paul N. Chaloux, Jr.
- 👤 Thomas F. Houghton
- 👤 Richard K. West
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 22:59
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/056
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
202 words
A method for forming simultaneously a level of interconnection conductors over and inter-level via studs through an insulating layer of a semiconductor chip, comprising the steps of: forming a plurality of via holes in a surface of said insulating layer disposed on said semiconductor chip; high-mobility sputtering a conductive material on to said surface of said insulating layer and into said via holes and including the steps of: substantially eliminating non-mobile sputter species in the vicinity of said surface of said insulating layer; sputtering at a sputter pressure of less than 7 microns, maintaining a chip bias level at a value that is above that needed for planarization of said conductive material but below the bias level where material focusing into the via holes occurs, and maintaining said surface of said insulating layer at a temperature above the temperature where conductive material planarization occurs, but below the temperature where phase changes occur for said conductive material or where device breakdown or hillock growth occurs; forming a mask over said sputtered surface to define areas of sputtered conductive material to be removed; and directing a particle beam on to said masked surface to remove conductive material from said areas defined by said mask.
Claim 2
Independent Claim
202 words
A method for forming simultaneously a level of interconnection conductors over and inter-level via studs through an insulating layer of a semiconductor chip, comprising the steps of: forming a plurality of via holes in a surface of said insulating layer disposed on said semiconductor chip; high-mobility sputtering a conductive material on to said surface of said insulating layer and into said via holes and including the steps of: substantially eliminating non-mobile sputter species in the vicinity of said surface of said insulating layer; sputtering at a sputter pressure of less than 7 microns, maintaining a chip bias level at a value that is above that needed for planarization of said conductive material but below the bias level where material focusing into the via holes occurs, and maintaining said surface of said insulating layer at a temperature above the temperature where conductive material planarization occurs, but below the temperature where phase changes occur for said conductive material or where device breakdown or hillock growth occurs; forming a mask over said sputtered surface to define areas of sputtered conductive material to be removed; and directing a particle beam on to said masked surface to remove conductive material from said areas defined by said mask.
Claim 3
Dependent Claim
31 words
A method as defined in claim 1, wherein said non-mobile species eliminating step comprises the step of maintaining a background pressure during sputtering that is less than to 10 -7 torr.
Claim 4
Dependent Claim
25 words
A method as defined in claim 1, wherein said sputtering step comprise the step of sputtering at a sputter pressure of less than 5.1 microns.
Claim 5
Dependent Claim
29 words
A method as defined in claim 1, wherein said bias level maintaining step comprises the step of maintaining said chip bias in the range of -125 to -300 volts.
Claim 6
Dependent Claim
24 words
A method as defined in claim 1, wherein, said sputtering step comprises the step of sputtering an Al alloy on to said insulating layer.
Claim 7
Dependent Claim
50 words
A method as defined in claim 1, wherein said surface temperature maintaining step comprises the step of maintaining said surface temperature at a temperature in the range of 350° C. to 500° C.; and wherein said sputtering step comprises the step of sputtering a conductive material of an Al alloy.
Claim 8
Dependent Claim
40 words
A method as defined in claim 1, wherein said sputtering step comprises the steps of: sputtering a layer of contact metallurgy over said insulating layer and into said via holes; and sputtering an Al alloy on to said contact metallurgy.
Claim 9
Dependent Claim
51 words
A method as defined in claim 1, wherein said via hole forming step comprise the steps of: forming an insulating layer of polyimide, forming a mask over said polyimide layer to define said plurality of via holes; etching to form said via holes in said polyimide layer; and removing said mask.
Claim 10
Dependent Claim
48 words
A method as defined in claim 8, wherein said non-mobile species eliminating step comprises the step of maintaining a background pressure during sputtering of less than 10 -7 Torr; and wherein said sputtering step comprises the step of sputtering at a sputter pressure of less than 5.1 microns.
Claim 11
Dependent Claim
29 words
A method as defined in claim 9, wherein said bias level maintaining step comprises the step of maintaining said chip bias in the range of -125 to -300 volts.
Claim 12
Dependent Claim
24 words
A method as defined in claim 10, wherein said sputtering step comprises the step of sputtering and Al alloy on to said insulating layer.
Claim 13
Dependent Claim
71 words
A method as defined in claim 1, wherein said via hole forming step comprises the steps of: forming an insulating layer of planar SiO 2 ; depositing a layer of plasma nitride on to said layer of planar SiO 2 ; forming a mask over said nitride layer; etching to form said via holes through said nitride layer and into said layer of planar SiO 2 ; and removing said mask.
Claim 14
Dependent Claim
48 words
A method as defined in claim 12, wherein said non-mobile species eliminating step comprises the step of maintaining a background pressure during sputtering of less than 10 -7 Torr; and wherein said sputtering step comprises the step of sputtering at a sputter pressure of less than 5.1 microns.
Claim 15
Dependent Claim
29 words
A method as defined in claim 13, wherein said bias level maintaining step comprises the step of maintaining said chip bias in the range of -125 to -300 volts.
Claim 16
Dependent Claim
24 words
A method as defined in claim 14, wherein said sputtering step comprises the step of sputtering an Al alloy on to said insulating layer.
References Cited (Backward Citations)
US3976524A
Cited
US4057476A
Cited
US4089766A
Cited
US4107726A
Cited
US4184909A
Cited
US4305801A
Cited
US4396458A
Cited
US4556897A
Cited
US4430365A
Cited
US4486946A
Cited
US4451326A
Cited
US4582563A
Cited
US4470874A
Cited
US4523372A
Cited
US4541169A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-01-25 | 1991-07-27 | 1992-01-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-01-25 | 1995-07-27 | 1996-01-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-01-25 | 1999-07-27 | 2000-01-26 | $7700.00 | Window Closed / Lapsed |