Method for forming conductive lines and vias

Claim 1

A method of fabricating on a multilayer interconnection ceramic body a metallurgical interconnection package for interconnection of a plurality of large scale integrated circuit semiconductor chips said ceramic body including an interconnection pattern and vias therein, the vias extending from said interconnection pattern and forming a planar surface with said ceramic body, said method comprising the steps of: depositing a blanket layer of conductive material on said planar surface; delineating said layer of conductive material into a circuit pattern connected to said vias; forming a mask which is resistive to reactive ion etching on the surface of said circuit pattern to define the area where the via studs are to be formed; subjecting to reactive ion etching unmasked areas of said circuit pattern to reduce the thickness of the circuit pattern and to form via studs; forming a dielectric material on said ceramic body; whereby said circuit pattern and via studs are formed as an integral structure from said blanket layer.

Claim 2

A method of fabricating on a multilayer interconnection ceramic body a metallurgical interconnection package for interconnection of a plurality of large scale integrated circuit semiconductor chips said ceramic body including an interconnection pattern and vias therein, the vias extending from said interconnection pattern and forming a planar surface with said ceramic body, said method comprising the steps of: depositing a blanket layer of conductive material on said planar surface; delineating said layer of conductive material into a circuit pattern connected to said vias; forming a mask which is resistive to reactive ion etching on the surface of said circuit pattern to define the area where the via studs are to be formed; subjecting to reactive ion etching unmasked areas of said circuit pattern to reduce the thickness of the circuit pattern and to form via studs; forming a dielectric material on said ceramic body; whereby said circuit pattern and via studs are formed as an integral structure from said blanket layer.

Claim 5

A method of fabricating on a multilayer ceramic substrate a metallurgical interconnection package for large scale integrated circuit semiconductor devices said substrate including multiple layers of conductive patterns and vias, the vias extending from said conductive patterns and forming a planar surface with said substrate, said method comprising the steps of: depositing a blanket layer of a conductive material on said planar surface of the substrate; forming a photoresist mask with openings to expose a desired metallurgical pattern connected to said vias; depositing a blanket layer of magnesium oxide over the photoresist mask and into its openings; removing the photoresist mask to lift-off overlying magnesium oxide to retain a magnesium oxide mask covering said desired metallurgical pattern; reactively ion etching the metallurgical pattern exposed by the magnesium oxide mask to form a precursor of said metallurgical pattern; removing said magnesium oxide mask; forming a new photoresist mask with openings defining desired via studs on said etched precursor metallurgical pattern; depositing a blanket magnesium oxide layer over the new photoresist mask and into the openings thereof; removing the new photoresist mask and overlying magnesium oxide to retain a new magnesium oxide mask at the desired via studs; reactively ion etching to form the via studs and the metallurgical interconnection pattern by removal of exposed precursor pattern not covered by the new magnesium oxide mask to the required thickness; forming a dielectric material over the metallurgical interconnection pattern to the height of the via studs; whereby is formed an integral structure of metallurgical via studs and interconnection pattern connected to said vias in the multilayer ceramic substrate.

Claim 6

A method of fabricating on a multilayer ceramic substrate a metallurgical interconnection package for large scale integrated circuit semiconductor devices said substrate including multiple layers of conductive patterns and vias, the vias extending from said conductive patterns and forming a planar surface with said substrate, said method comprising the steps of: depositing a blanket layer of a conductive material on said planar surface of the substrate; forming a photoresist mask with openings to expose a desired metallurgical pattern connected to said vias; depositing a blanket layer of magnesium oxide over the photoresist mask and into its openings; removing the photoresist mask to lift-off overlying magnesium oxide to retain a magnesium oxide mask covering said desired metallurgical pattern; reactively ion etching the metallurgical pattern exposed by the magnesium oxide mask to form a precursor of said metallurgical pattern; removing said magnesium oxide mask; forming a new photoresist mask with openings defining desired via studs on said etched precursor metallurgical pattern; depositing a blanket magnesium oxide layer over the new photoresist mask and into the openings thereof; removing the new photoresist mask and overlying magnesium oxide to retain a new magnesium oxide mask at the desired via studs; reactively ion etching to form the via studs and the metallurgical interconnection pattern by removal of exposed precursor pattern not covered by the new magnesium oxide mask to the required thickness; forming a dielectric material over the metallurgical interconnection pattern to the height of the via studs; whereby is formed an integral structure of metallurgical via studs and interconnection pattern connected to said vias in the multilayer ceramic substrate.