US5013687A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Framed chip hybrid stacked layer assembly
Assignee: Grumman Corp
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Filing: 1989-07-27
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Granted: 1991-05-07
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Expires: 2009-07-27
Abstract
Abstract A stacked integrated circuit assembly and method of fabricating the same are disclosed. The assembly includes a plurality of insulating substrate layers each supporting one or more embedded integrated circuit chips. The substrates each incorporate substantially identical conductive patterns formed on the insulating layer surface and/or on an insulating film that covers the substrate. A plurality of apertures are then formed which intersect the patterns, followed by insertion of IC chips into the apertures. The insulating layer is then cut to form a plurality of segments which are subsequently stacked vertically to form a module.
Inventors
- 👤 Allen L. Solomon
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 11:06
CPC Classifications
H; H10; H10W; H10W70/00; H10W70/60; H10W70/611; H10W90/00; H10W90/401; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49124; Y10T29/4913; Y10T29/49133; Y10T29/49135; Y10T29/49139
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
103 words
A method of forming a multi-layer module comprising: forming a plurality of substantially identical conductive patterns on a first surface of an insulating wafer; forming a plurality of apertures in the insulating wafer, each of said apertures intersecting a dedicated one of the plurality of conductive patterns; inserting an integrated circuit chip within each of the apertures; electrically connecting the integrated circuit chip to a dedicated portion of the conductive pattern; cutting the insulating layer to form a plurality of layer segments; and vertically stacking the segments such-that the integrated circuits and conductive patterns are in substantial vertical registration to form a module.
Claim 2
Independent Claim
103 words
A method of forming a multi-layer module comprising: forming a plurality of substantially identical conductive patterns on a first surface of an insulating wafer; forming a plurality of apertures in the insulating wafer, each of said apertures intersecting a dedicated one of the plurality of conductive patterns; inserting an integrated circuit chip within each of the apertures; electrically connecting the integrated circuit chip to a dedicated portion of the conductive pattern; cutting the insulating layer to form a plurality of layer segments; and vertically stacking the segments such-that the integrated circuits and conductive patterns are in substantial vertical registration to form a module.
Claim 3
Dependent Claim
56 words
The method as recited in claim 1 further comprising the step of: forming a first portion of the conductive pattern upon the surface of the substrate; forming an insulating layer upon the substrate, the integrated circuit chip and the conductive pattern first portion; and forming a second portion of the conductive pattern upon the insulating layer.
Claim 4
Dependent Claim
22 words
The method as recited in claim 2 further comprising the step of connecting the first and second portions of the conductive pattern.
Claim 5
Dependent Claim
35 words
The method as recited in claim 3 further comprising the step of selectively removing a portion of the insulating layer prior to connecting the second portion of the conductive pattern to the integrated circuit chip.
Claim 6
Dependent Claim
40 words
The method as recited in claim 1 further comprising the step of forming conductive pads on a first vertical edge portion of the layer segments to facilitate abutting electrical connection between the module and a planar array of photodector elements.
Claim 7
Dependent Claim
20 words
The method as recited in claim 1 further comprising the step of adhesively bonding the integrated circuits within the apertures.
Claim 8
Dependent Claim
36 words
The method as recited in claim 1 further comprising forming conductive pads on second vertical edge surfaces of the layer segments for communicating electrical communication between the integrated circuits and external control and signal processing circuitry.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-05-06 | 1994-11-05 | 1995-05-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-05-06 | 1998-11-05 | 1999-05-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-05-06 | 2002-11-05 | 2003-05-07 | $7700.00 | Window Closed / Lapsed |