3-D integrated circuit assembly employing discrete chips

Claim 2

An integrated circuit (IC) assembly, comprising: a plurality of stacked IC layers, each layer comprising; a substrate having a plurality of recesses extending in from one surface thereof, and a plurality if IC chips retained in respective recesses in said substrate, said substrate being formed from a material that is generally thermally matched with said IC chips, a plurality of conductive feedthroughs extending through the substrate between said one surface and an opposite substrate surface, and connector means electrically connecting said IC chips to said feedthroughs along said one surface of the substrate, said feedthroughs providing electrical paths between said chips and said opposite substrate surface; and means including micro-bridge connector springs on said surfaces of the substrate to enable the substrate to make electrical contact with the substrates immediately above and below.

Claim 3

The IC assembly of claim 1, wherein said IC chips are formed from silicon, and said substrate is formed from a material selected from the group consisting of silicon and aluminum nitride.

Claim 4

A 3-D integrated circuit (IC) assembly, comprising: a plurality of stacked IC layers, each layer comprising: a substrate having first and second opposed surfaces, and a plurality of recesses extending into the substrate from the first surface, a plurality of IC chips retained in respective recesses in the substrate, a plurality of conductive feedthroughs extending through the substrate between said first and second surfaces, connector means electrically connecting said IC chips to said feedthroughs along the first surface side of the substrate, said feedthroughs providing electrical paths between said chips and the opposite side of the substrate, and a network of conductive connections interconnecting said feedthroughs adjacent said second substrate surface, means retaining said layers in a stack with their substrates mutually aligned and spaced apart from each other, and interlayer connector means electrically connecting selected locations on the IC chips with selected facing locations on the conductive interconnection network of the adjacent layer.

Claim 5

A 3-D integrated circuit (IC) assembly, comprising: a plurality of stacked IC layers, each layer comprising: a substrate having first and second opposed surfaces, and a plurality of recesses extending into the substrate from the first surface, a plurality of IC chips retained in respective recesses in the substrate, a plurality of conductive feedthroughs extending through the substrate between said first and second surfaces, connector means electrically connecting said IC chips to said feedthroughs along the first surface side of the substrate, said feedthroughs providing electrical paths between said chips and the opposite side of the substrate, and a network of conductive connections interconnecting said feedthroughs adjacent said second substrate surface, means retaining said layers in a stack with their substrates mutually aligned and spaced apart from each other, and interlayer connector means electrically connecting selected locations on the IC chips with selected facing locations on the conductive interconnection network of the adjacent layer.

Claim 6

The 3-D assembly of claim 3, said interlayer connector means comprising bridge springs on the IC chip sides of the substrates bearing against opposed bridge springs on the facing conductive interconnection network of the adjacent layer.

Claim 7

The 3-D IC assembly of claim 3, the network for each IC layer comprising a series of alternating conductive and non-conductive network layers.

Claim 8

The 3-D IC assembly of claim 5, wherein said conductive network layers are photolithographically patterned to establish desired interconnections between said IC chips.

Claim 9

The 3-D IC assembly of claim 3, wherein said substrates are formed from a material that is generally thermally matched with their respective IC chips.

Claim 10

The 3-D IC assembly of claim 7, wherein said IC chips are formed from silicon, said substrates are formed from a material selected from the group consisting of silicon and aluminum nitride.

Claim 11

A 3-D integrated circuit (IC) assembly, comprising: a plurality of stacked IC layers, each layer comprising: a substrate having first and second opposed surfaces, an IC network disposed generally along the first substrate surface, a plurality of electrically conductive feedthroughs extending through the substrate between said first and second surfaces, connector means electrically connecting selected locations in said IC network to said feedthroughs from the first surface side thereof, said feedthroughs providing electrical paths between said IC network and the opposite side of the substrate, and a network of conductive connectors between said feedthroughs adjacent said second substrate surface, means retaining said layers in a stack with their substrates mutually aligned and spaced apart from each other, and interlayer connector means electrically connecting selected locations on the IC chips with selected facing locations on the conductive interconnection network of the adjacent layer.

Claim 12

A 3-D integrated circuit (IC) assembly, comprising: a plurality of stacked IC layers, each layer comprising: a substrate having first and second opposed surfaces, an IC network disposed generally along the first substrate surface, a plurality of electrically conductive feedthroughs extending through the substrate between said first and second surfaces, connector means electrically connecting selected locations in said IC network to said feedthroughs from the first surface side thereof, said feedthroughs providing electrical paths between said IC network and the opposite side of the substrate, and a network of conductive connectors between said feedthroughs adjacent said second substrate surface, means retaining said layers in a stack with their substrates mutually aligned and spaced apart from each other, and interlayer connector means electrically connecting selected locations on the IC chips with selected facing locations on the conductive interconnection network of the adjacent layer.

Claim 13

The 3-D assembly of claim 9, said interlayer connector means comprising bridge springs on the IC chip sides of the substrates bearing against bridge springs on the facing conductive interconnection network of the adjacent layer.

Claim 14

The 3-D IC assembly of claim 9, the network for each IC layer comprising a series of alternating conductive and non-conductive network layers.

Claim 15

The IC assembly of claim 11, wherein said conductive network layers are photolithographically patterned to establish desired interconnections between said IC chips.