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Method and system for screening reliability of semiconductor circuits

Assignee: Texas Instruments Inc
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Filing: 1995-06-07
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Granted: 1997-04-01
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Expires: 2015-06-07
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Abstract

Abstract A method and system for screening semiconductor circuits is disclosed herein. A circuit 50, such as an SOI circuit, is provided. The circuit includes a plurality of transistors and is coupled to a supply voltage node V DD , a reference node V SS , and a substrate node V SUB . A supply voltage is applied to the supply node while a reference voltage is applied to the reference node and a test voltage is applied to the substrate node. The current I DD flowing to the supply and/or reference node is then measured. These steps are repeated for a plurality of test circuits to determine at least one performance and/or reliability criterion. The steps can then be repeated to screen other circuits by comparing the measured current to the reliability limit(s).

Inventors

  • 👤 Theodore W. Houston

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 14:34
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/316; G01R31/3163

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 107 words
A system for testing a semiconductor which includes a circuit having a plurality of transistors, said circuit further including a supply voltage node, a reference node and a substrate node, said system comprising: circuitry for applying a supply voltage to said supply voltage node of said circuit; circuitry for applying a reference voltage to said reference node of said circuit; circuitry for applying a test voltage to said substrate node of said circuit; circuitry for measuring a current flowing to said supply node such that the current flowing to the supply node can be compared to a predetermined current criterion to obtain performance information about said circuit.
Claim 2
Independent Claim 107 words
A system for testing a semiconductor which includes a circuit having a plurality of transistors, said circuit further including a supply voltage node, a reference node and a substrate node, said system comprising: circuitry for applying a supply voltage to said supply voltage node of said circuit; circuitry for applying a reference voltage to said reference node of said circuit; circuitry for applying a test voltage to said substrate node of said circuit; circuitry for measuring a current flowing to said supply node such that the current flowing to the supply node can be compared to a predetermined current criterion to obtain performance information about said circuit.
Claim 3
Dependent Claim 17 words
The system of claim 1 wherein said performance information comprises information on radiation hardness of said circuit.
Claim 4
Dependent Claim 17 words
The system of claim 1 wherein said performance information comprises information on the reliability of said circuit.
Claim 5
Dependent Claim 12 words
The system of claim 1 wherein said circuit comprises a silicon-on-insulator circuit.
Claim 6
Dependent Claim 25 words
The system of claim 1 wherein said system for testing comprises a system for performing a screening test prior to packaging of said semiconductor circuit.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2000-03-31 2000-09-30 2001-04-01 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2004-03-31 2004-09-30 2005-04-01 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2008-03-31 2008-09-30 2009-04-01 $7700.00 Window Closed / Lapsed

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