US5097206A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Built-in test circuit for static CMOS circuits
Assignee: HP Inc
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Filing: 1990-10-05
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Granted: 1992-03-17
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Expires: 2010-10-05
Abstract
Abstract A built-in test circuit configuration for row based static CMOS integrated circuits using a control circuit and a plurality of switching circuits, each connecting VDD to a row power buss through a large pass transistor during normal operating modes and through a low current pull up transistor during the test mode of operation. Defect induced currents are detected by the OR'd outputs of the switching circuits connected to an OR function formed in the control circuit. Additional switching circuits are provided for supplying multiple main power supplies to each integrated circuit row. The switching and additional switching circuits may be physically configured beneath row end caps.
Inventors
- 👤 Frederick A. Perner
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 16:19
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/30; G01R31/3004; G11; G11C; G11C29/00; G11C29/04; G11C29/50; G11C2029/5006
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
129 words
An integrated circuit with built-in current testing, comprising: a plurality of rows of circuit components; main power buss means for distributing power within the integrated circuit; row power buss means for applying power from the main power buss means to each of said plurality of rows of circuit components in the integrated circuit; switching circuit means in the integrated circuit operable in a normal mode to provide a connection between the main and row power buss means and operable in a test mode to substantially isolate the main power buss means from the row power buss means; and control circuit means in the integrated circuit responsive to a predetermined voltage differential between the main and row power buss means in the test mode the detecting defect induced currents therein.
Claim 2
Dependent Claim
129 words
An integrated circuit with built-in current testing, comprising: a plurality of rows of circuit components; main power buss means for distributing power within the integrated circuit; row power buss means for applying power from the main power buss means to each of said plurality of rows of circuit components in the integrated circuit; switching circuit means in the integrated circuit operable in a normal mode to provide a connection between the main and row power buss means and operable in a test mode to substantially isolate the main power buss means from the row power buss means; and control circuit means in the integrated circuit responsive to a predetermined voltage differential between the main and row power buss means in the test mode the detecting defect induced currents therein.
Claim 3
Dependent Claim
58 words
The integrated circuit claimed in claim 1, wherein the switching circuit means further comprises: pass transistor means operable in the normal mode to provide a low impedance connection between main and row power buss means; and pull up transistor means operable in the test mode to provide a high impedance connection between main and row power buss means.
Claim 4
Dependent Claim
59 words
The integrated circuit claimed in claim 1, wherein the control circuit means further comprises: a plurality of voltage sensitive switching circuits, each associated with a different portion of the integrated circuit; and OR function means for detecting defect induced currents in any of the portions of the integrated circuit in response to one of the plurality of switching circuits.
Claim 5
Dependent Claim
53 words
The integrated circuit claimed in claim 1, further comprising: additional main power buss means for providing additional supply voltages; and additional switching circuit means associated with each portion of the integrated circuit requiring more than one supply voltage for connecting the additional main power buss means thereto during the normal mode of operation.
Claim 6
Independent Claim
101 words
A method of testing an integrated circuit for defect induced currents comprising the steps of: applying a supply voltage to the integrated circuit; applying power during a normal mode from the supply voltage to a plurality of circuit components in the integrated circuit through a switching circuit in the integrated circuit; operating the switching circuit in a test mode in which the plurality of circuit components are substantially isolated from the supply voltage; and detecting defect induced currents in the integrated circuit in response to a predetermined voltage differential between the supply voltage and the circuit components during the test mode.
Claim 7
Independent Claim
101 words
A method of testing an integrated circuit for defect induced currents comprising the steps of: applying a supply voltage to the integrated circuit; applying power during a normal mode from the supply voltage to a plurality of circuit components in the integrated circuit through a switching circuit in the integrated circuit; operating the switching circuit in a test mode in which the plurality of circuit components are substantially isolated from the supply voltage; and detecting defect induced currents in the integrated circuit in response to a predetermined voltage differential between the supply voltage and the circuit components during the test mode.
Claim 8
Dependent Claim
69 words
The method of testing an integrated circuit claimed in claim 5, further comprising the steps of: biasing a pass transistor to conduct in the normal mode to provide a low impedance connection between supply voltage and the plurality of circuit components; and biasing a pull up transistor into conduction to provide a high impedance connection between the supply voltage and the plurality of circuit components during the test mode.
Claim 9
Dependent Claim
87 words
The method of testing an integrated circuit claimed in claim 5 wherein the step of detecting defect induced currents further comprises the steps of: providing a plurality of switching circuits, each associated with a different portion of the circuit components in the integrated circuit; and detecting defect induced currents in any of the portions of the integrated circuit associated with the plurality of switching circuits in response to the predetermined voltage differential between the supply voltage and that portion of the integrated circuit during the test mode.
Claim 10
Dependent Claim
37 words
The method of testing an integrated circuit claimed in claim 5, further comprising the steps of: connecting additional supply voltages to some portions of the integrated circuit through additional switching circuits during the normal mode of operation.
Claim 11
Dependent Claim
64 words
The integrated circuit claimed in claim 3 wherein the integrated circuit is a static CMOS logic circuit in which the logic signals do not change during the test mode and each of the voltage sensitive switching circuits further comprises: a transistor connected between the row and power buss means for operation in response to a voltage differential of about one transistor threshold voltage drop.
Claim 12
Dependent Claim
73 words
The method of testing an integrated circuit claimed in claim 7 wherein the integrated circuit is a static CMOS logic circuit in which the logic signals do not change during the test mode and the step of detecting defect induced currents further comprises the step of: connecting a transistor between the supply voltage and the circuit components for operation in response to a voltage differential therebetween of about one transistor threshold voltage drop.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-03-17 | 1995-09-16 | 1996-03-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-03-17 | 1999-09-16 | 2000-03-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-03-17 | 2003-09-16 | 2004-03-17 | $7700.00 | Window Closed / Lapsed |