Method for reliability testing of integrated circuits

Claim 1

A method for reliability testing of wafer stage integrated circuits comprising, (a) electrically aging wafer stage integrated circuits each having at least one MOSFET, different MOSFETs having different dimensions, the aging involving empirically measuring a radiation hardness factor, H, where H is a known function of device lifetime, device current and device dimensions, until failure of said MOSFET, (b) simulating the aging of wafer stage integrated circuits each having at least one MOSFET by applying a dose of ionizing radiation sufficient to cause interface trap degradation failure, (c) correlating the ionizing radiation dose causing device failure to the hardness factor H and predicting device lifetime.

Claim 2

A method for reliability testing of wafer stage integrated circuits comprising, (a) electrically aging wafer stage integrated circuits each having at least one MOSFET, different MOSFETs having different dimensions, the aging involving empirically measuring a radiation hardness factor, H, where H is a known function of device lifetime, device current and device dimensions, until failure of said MOSFET, (b) simulating the aging of wafer stage integrated circuits each having at least one MOSFET by applying a dose of ionizing radiation sufficient to cause interface trap degradation failure, (c) correlating the ionizing radiation dose causing device failure to the hardness factor H and predicting device lifetime.

Claim 6

A method for reliability testing of wafer stage integrated circuits comprising, (a) measuring substrate currents and lifetimes attributable to interface trap degradation in MOSFETs each having a gate, source, drain, at least one MOSFET being part of an integrated circuit on a wafer, different MOSFETs being made by different processes and having different dimensions, including a width dimension, (b) relating device substrate currents to device lifetimes attributable to interface trap degradation for devices of different widths and establishing device hardness factors, H, which are functions of substrate current, width and device lifetimes, (c) directing a beam of ionizing radiation onto an integrated circuit device within a wafer, the device having a MOSFET with at least one oxide layer, the beam having sufficient energy to generate ionization induced electron-hole pairs in said oxide layer, (d) measuring a critical radiation dose D crit , versus hardness factor, H, where D crit is the radiation dose producing a number of interface traps causing the MOSFET in said device to become inoperative, and (e) predicting device lifetime based upon values of D crit .

Claim 7

A method for reliability testing of wafer stage integrated circuits comprising, (a) measuring substrate currents and lifetimes attributable to interface trap degradation in MOSFETs each having a gate, source, drain, at least one MOSFET being part of an integrated circuit on a wafer, different MOSFETs being made by different processes and having different dimensions, including a width dimension, (b) relating device substrate currents to device lifetimes attributable to interface trap degradation for devices of different widths and establishing device hardness factors, H, which are functions of substrate current, width and device lifetimes, (c) directing a beam of ionizing radiation onto an integrated circuit device within a wafer, the device having a MOSFET with at least one oxide layer, the beam having sufficient energy to generate ionization induced electron-hole pairs in said oxide layer, (d) measuring a critical radiation dose D crit , versus hardness factor, H, where D crit is the radiation dose producing a number of interface traps causing the MOSFET in said device to become inoperative, and (e) predicting device lifetime based upon values of D crit .