US5057774A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Apparatus for measuring the quiescent current of an integrated monolithic digital circuit
Assignee: NXP BV
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Filing: 1990-01-09
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Granted: 1991-10-15
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Expires: 2010-01-09
Abstract
Abstract An arrangement for measuring the quiescent current of a digital IC includes a current sensor connected in series with the IC and the voltage supply, a voltage stabilization circuit for stabilizing the voltage across the IC and a signal processing circuit coupled thereto for processing the measured quiescent current. The quiescent current is measured when no flip-flops are switched in the IC. By means of the arrangement, it is possible to measure rapidly and accurately whether the quiescent current assumes an abnormal value, which indicates that the IC contains defects. The signal processing circuit may include a current mirror which is coupled to a current comparator circuit supplying a digital output signal for determining the existence of a defect.
Inventors
- 👤 Sebastiaan C. Verhelst
- 👤 Evert Seevinck
- 👤 Keith Baker
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 20:54
CPC Classifications
G; G01; G01R; G01R19/00; G01R19/145; G01R19/15; G01R31/00; G01R31/28; G01R31/30; G01R31/3004
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
89 words
An arrangement for measuring a quiescent current of an integrated monolithic digital circuit comprising a transistor current sensor for receiving the IC quiescent current and which includes a first connection terminal for coupling to a supply terminal of the integrated monolithic circuit and with a voltage second connection terminal for coupling to a supply, characterized in that the arrangement comprises voltage stabilization means for stabilizing a voltage at the first connection terminal and signal processing means coupled to the voltage stabilization means for signal processing of the quiescent current.
Claim 2
Dependent Claim
89 words
An arrangement for measuring a quiescent current of an integrated monolithic digital circuit comprising a transistor current sensor for receiving the IC quiescent current and which includes a first connection terminal for coupling to a supply terminal of the integrated monolithic circuit and with a voltage second connection terminal for coupling to a supply, characterized in that the arrangement comprises voltage stabilization means for stabilizing a voltage at the first connection terminal and signal processing means coupled to the voltage stabilization means for signal processing of the quiescent current.
Claim 3
Dependent Claim
60 words
An arrangement as claimed in claim 1, wherein the voltage stabilization means comprise a differential amplifier having a first input coupled to the first connection terminal, a second input coupled to the second connection terminal or to a connection terminal for connection to a reference voltage source, and an output coupled to a control electrode of the transistor current sensor.
Claim 4
Dependent Claim
53 words
An arrangement as claimed in claim 2, wherein the output of the differential amplifier is coupled to the transistor control electrode via a modification circuit for modifying the operation of the transistor current sensor outside of a quiescent current measuring period or outside of a quiescent current measurement of the integrated monolithic circuit.
Claim 5
Dependent Claim
20 words
An arrangement as claimed in claim 3, wherein the modification circuit controls the transistor current sensor to be fully conductive.
Claim 6
Dependent Claim
50 words
An arrangement as claimed in claim 1, wherein the signal processing means comprises a first transistor which, together with the transistor current sensor form a current mirror configuration which supplies, via an output electrode of the first transistor, a current which is a mirror image of the IC quiescent current.
Claim 7
Dependent Claim
83 words
An arrangement as claimed in claim 5, wherein the signal processing means comprise a differential amplifier having a first input coupler to the first connection terminal, a second input coupled to the output electrode of the first transistor and an output coupled to a control electrode of a second transistor, said second transistor having a first output electrode coupled to the output electrode of the first transistor, and wherein a second output electrode of said second transistor supplies a further processed quiescent current.
Claim 8
Dependent Claim
46 words
An arrangement as claimed in claim 6, wherein the signal processing means comprise further transistors connected so as to constitute with the transistor current sensor a current mirror configuration for obtaining further processed quiescent currents, the transistors of the signal processing means having different geometric dimensions.
Claim 9
Dependent Claim
49 words
An arrangement as claimed in claim 1 which further comprises comparison means coupled to the signal processing means for comparing a processed quiescent current with at least one reference current or reference voltage, the comparison means being arranged to indicate when the reference current or reference voltage is exceeded.
Claim 10
Dependent Claim
65 words
An arrangement as claimed in claim 8, wherein the comparison means comprise at least one current mirror configuration having a first input for the supply of a processed quiescent current, a second input for the supply of a reference current and a digital output which assumes, in dependence upon the processes quiescent currents with respect to the reference currents, a first and a second value.
Claim 11
Dependent Claim
17 words
An arrangement as claimed in claim 8, wherein the comparison means comprise an analog voltage comparison means.
Claim 12
Dependent Claim
20 words
An arrangement as claimed in claim 8, wherein an output of the comparison means is coupled to a scan chain.
Claim 13
Dependent Claim
20 words
An arrangement as claimed in claim 8, wherein the output of the comparison means is coupled to a self-test circuit.
Claim 14
Dependent Claim
46 words
An integrated monolithic digital circuit comprising at least one subcircuit, wherein the integrated monolithic circuit comprises at least one arrangement or at least a part thereof as claimed in claim 1 for measuring the quiescent current of subcircuits, of combinations of subcircuits or of all subcircuits.
Claim 15
Dependent Claim
45 words
An integrated monolithic digital circuit comprising an arrangement as claimed in claim 1, and a boundary scan logic circuit for testing integrated circuits on printed circuit boards, in which the quiescent current measuring arrangement and the boundary scan logic circuit are coupled to each other.
Claim 16
Dependent Claim
33 words
A testing apparatus for measuring a quiescent current of an integrated monolithic digital circuit characterized in that the testing apparatus comprises at least a part of the arrangement as claimed in claim 1.
Claim 17
Dependent Claim
82 words
An arrangement as claimed in claim 1, wherein the voltage stabilization means comprise a differential amplifier having a first input coupled to the first connection terminal and a second input coupled to a reference voltage point, and means coupling an output of the differential amplifier to the transistor control electrode via a modification circuit for modifying the operation of the transistor current sensor outside of a quiescent current measuring period or outside of a quiescent current measurement of the integrated monolithic circuit.
Claim 18
Dependent Claim
50 words
An arrangement as claimed in claim 2, wherein the signal processing means comprise a first transistor which, together with the transistor current sensor form a current mirror configuration which supplies, via an output electrode of the first transistor, a current which is a mirror image of the IC quiescent current.
Claim 19
Dependent Claim
109 words
Apparatus for testing an integrated monolithic digital circuit comprising: a transistor current sensor for receiving a quiescent current of aid integrated circuit, circuit means including first and second connection terminals for coupling the transistor current sensor to a supply terminal of said integrated circuit and to a voltage supply terminal, respectively, voltage stabilization means coupled in a feedback circuit between said first connection terminal and a control electrode of the transistor current sensor for stabilizing the voltage at the first connection terminal, and signal processing means coupled to said circuit means for processing said quiescent current so as to provide an indication of the condition of said integrated circuit.
Claim 20
Dependent Claim
109 words
Apparatus for testing an integrated monolithic digital circuit comprising: a transistor current sensor for receiving a quiescent current of aid integrated circuit, circuit means including first and second connection terminals for coupling the transistor current sensor to a supply terminal of said integrated circuit and to a voltage supply terminal, respectively, voltage stabilization means coupled in a feedback circuit between said first connection terminal and a control electrode of the transistor current sensor for stabilizing the voltage at the first connection terminal, and signal processing means coupled to said circuit means for processing said quiescent current so as to provide an indication of the condition of said integrated circuit.
Claim 21
Dependent Claim
131 words
A testing apparatus as claimed in claim 18, wherein, the voltage stabilization means comprise a first differential amplifier having first and second inputs coupled to the first connection terminal and to a point of reference voltage, respectively, and an output coupled to the control electrode of the transistor current sensor, and said signal processing means comprise first and second transistors connected in series between said second connection terminal and an output of the signal processing means, a second differential amplifier having first and second inputs coupled to the first connection terminal and to an output electrode of the first transistor, respectively, and an output coupled to a control electrode of the second transistor, and means coupling said current sensor transistor and said first transistor together to form a current mirror circuit.
Claim 22
Dependent Claim
115 words
A testing apparatus as claimed in claim 18 wherein; said circuit means connect said transistor current sensor in series circuit with said integrated monolithic digital circuit between said voltage supply terminal and a further voltage supply terminal for the integrated circuit, said signal processing means includes a first field effect transistor and said transistor current sensor comprises a second field effect transistor, and said circuit means couples said first and second field effect transistors together so as to form a current mirror circuit having an output which supplies an output current determined by the current flowing through the transistor current sensor and which output current provides said indication of the condition of said integrated circuit.
Claim 23
Dependent Claim
33 words
A current measuring arrangement as claimed in claim 1 wherein said voltage stabilization means comprise a feedback circuit coupled between said first connection terminal and a control terminal for said transistor current sensor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-10-14 | 1995-04-15 | 1995-10-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-10-14 | 1999-04-15 | 1999-10-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-10-14 | 2003-04-15 | 2003-10-15 | $7700.00 | Window Closed / Lapsed |