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US4860261A
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Leakage verification for flash EPROM
Assignee: Intel Corp
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Filing: 1989-03-14
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Granted: 1989-08-22
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Expires: 2009-03-14
Abstract
Abstract A circuit and method for verifying leakage in a flash EPROM/EEPROM memory cell which is fabricated on a silicon substrate having floating gate. A word line coupled to the control gate of the memory cell is typically at ground potential, but during a test mode a positive voltage is placed on the control gate and leakage current at the drain is measured. A good cell will typically have zero or negligible drain leakage current, however, a cell which is susceptible to being overerased will exhibit appreciable leakage current. A circuit is implemented on the chip with the memory for switching a positive voltage onto the word line during the test mode.
Inventors
- 👤 Jerry A. Kreifels
- 👤 George Hoekstra
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 03:27
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/34; G11C16/3436; G11C16/344; G11C16/345; G11C29/00; G11C29/02; G11C29/025; G11C29/04; G11C29/50; G11C16/04; G11C2029/5006
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
69 words
A method for determining if an electrically erasable and electrically programmable read-only memory having a plurality of memory cells which each has a floating gate, comprising the steps of: placing a small positive voltage on control gates of said memory cells; measuring leakage current at drains of said memory cells; and determining if leakage current exceeds a predetermined value, which is an indication of susceptibility to an overerase condition.
Claim 2
Independent Claim
69 words
A method for determining if an electrically erasable and electrically programmable read-only memory having a plurality of memory cells which each has a floating gate, comprising the steps of: placing a small positive voltage on control gates of said memory cells; measuring leakage current at drains of said memory cells; and determining if leakage current exceeds a predetermined value, which is an indication of susceptibility to an overerase condition.
References Cited (Backward Citations)
US4797586A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-08-21 | 1993-02-20 | 1993-08-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-08-21 | 1997-02-20 | 1997-08-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-08-21 | 2001-02-20 | 2001-08-22 | $7700.00 | Window Closed / Lapsed |