Patent US5583061A successfully refreshed from Google Patents.
US5583061A
Expired / Lapsed
US
⏱️ 0.0 years remaining
PMOS transistors with different breakdown voltages formed in the same substrate
Assignee: Vishay Siliconix Inc
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Filing: 1995-06-05
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Granted: 1996-12-10
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Expires: 2015-06-05
Abstract
Abstract A process is disclosed (hereafter referred to as the "BiCDMOS Process") which simultaneously forms bipolar transistors, relatively high voltage CMOS transistors, relatively low voltage CMOS transistors, DMOS transistors, zener diodes, and thin-film resistors, or any desired combination of these, all on the same integrated circuit chip. The process uses a small number of masking steps, forms high performance transistor structures, and results in a high yield of functioning die. Isolation structures, bipolar transistor structures, CMOS transistor structures, DMOS transistor structures, zener diode structures, and thin-film resistor structures are also disclosed.
Inventors
- 👤 Richard K. Williams
- 👤 Hamza Yilmaz
- 👤 Michael E. Cornell
- 👤 Jun W. Chen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 15:28
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/64; H10D30/65; H10D10/00; H10D10/01; H10D10/051; H10D10/40; H10D10/421; H10D30/601; H10D30/603; H10D30/66; H10D30/663; H10D62/00; H10D62/10; H10D62/17; H10D62/177; H10D84/00; H10D84/01; H10D84/0107; H10D84/0109; H10D84/02; H10D84/03; H10D84/038; H10D84/40; H10D84/401; H10D84/403; H10D62/13; H10D62/149; H10D62/151; H10D62/156; H10D62/157; Y; Y10; Y10S; Y10S148/00; Y10S148/082; Y10S148/126; Y10S438/00; Y10S438/983
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
218 words
A method for forming at least two PMOS transistors having different intended breakdown voltages, said method comprising the steps of: forming a first gate of a first PMOS transistor, said first gate having a length of approximately 2 microns to achieve a first breakdown voltage; forming a second gate of a second PMOS transistor, said second gate having a length of approximately 2.5 microns to achieve a higher breakdown voltage than said first breakdown voltage; implanting P-type dopants at a first energy and a first dosage using a first mask to form source and drain regions for said first PMOS transistor and said second PMOS transistor, said first energy being insufficient to cause said dopants to penetrate through said gate, said source and drain regions being self-aligned with said first gate and said second gate; and implanting P-type dopants through said first gate and said second gate at a second energy higher than said first energy and a second dosage lower than said first dosage to adjust a threshold voltage of said first PMOS transistor and said second PMOS transistor such that said first PMOS transistor and said second PMOS transistor are formed using the same process steps, said step of implanting P-type dopants through said first gate and said second gate being conducted using said first mask.
Claim 2
Independent Claim
218 words
A method for forming at least two PMOS transistors having different intended breakdown voltages, said method comprising the steps of: forming a first gate of a first PMOS transistor, said first gate having a length of approximately 2 microns to achieve a first breakdown voltage; forming a second gate of a second PMOS transistor, said second gate having a length of approximately 2.5 microns to achieve a higher breakdown voltage than said first breakdown voltage; implanting P-type dopants at a first energy and a first dosage using a first mask to form source and drain regions for said first PMOS transistor and said second PMOS transistor, said first energy being insufficient to cause said dopants to penetrate through said gate, said source and drain regions being self-aligned with said first gate and said second gate; and implanting P-type dopants through said first gate and said second gate at a second energy higher than said first energy and a second dosage lower than said first dosage to adjust a threshold voltage of said first PMOS transistor and said second PMOS transistor such that said first PMOS transistor and said second PMOS transistor are formed using the same process steps, said step of implanting P-type dopants through said first gate and said second gate being conducted using said first mask.
Claim 3
Dependent Claim
34 words
The method of claim 1 wherein said first PMOS transistor exhibits a breakdown voltage less than approximately 12 volts, and said second PMOS transistor exhibits a breakdown voltage of greater than approximately 15 volts.
References Cited (Backward Citations)
US4119440A
Cited
US4403395A
Cited
US4481706A
Cited
US4826780A
Cited
US4590664A
Cited
US4601760A
Cited
US4628341A
Cited
US4887142A
Cited
US4795716A
Cited
JPH0230187A
Cited
US5156989A
Cited
US5091760A
Cited
US5091328A
Cited
JPH03203377A
Cited
US5260228A
Cited
US5262345A
Cited
US5091324A
Cited
US5171699A
Cited
US5158463A
Cited
US5336624A
Cited
US5179432A
Cited
US5243214A
Cited
US5254487A
Cited
US5407849A
Cited
US5468666A
Cited
US5472887A
Cited
US5432114A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-12-10 | 2000-06-10 | 2000-12-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-12-10 | 2004-06-10 | 2004-12-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-12-10 | 2008-06-10 | 2008-12-10 | $7700.00 | Window Closed / Lapsed |