US5091328A
Expired / Lapsed
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Method of late programming MOS devices
Assignee: National Semiconductor Corp
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Filing: 1989-11-21
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Granted: 1992-02-25
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Expires: 2009-11-21
Abstract
Abstract Method for late programming of MOS integrated circuit devices. A second or third level conductive layer is used as a device selection mask for transporting dopant from a doped gate (formed from a first level conductive layer) into the channel region of selected field effect transistors.
Inventors
- 👤 William E. Miller
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 00:46
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/064; H10D; H10D84/00; H10D84/90; H10D84/903; Y; Y10; Y10S; Y10S438/00; Y10S438/914; Y10S438/923
Claims Analysis
Total Claims: 38
Claim 1
Independent Claim
143 words
A method for late programming integrated circuits, comprising the steps: a) forming on a silicon wafer, a field effect transistor, having a channel region defined by a source and drain, self-aligned to a gate formed from a first level conductive layer that is doped with dopant; b) depositing a first insulating layer, having an upper surface, over said field effect transistor; c) opening contact windows in said first insulating layer over said source and said drain; d) depositing a second level conductive layer on said upper surface of first insulating layer thereby filling said contact windows to make a low resistance electrical connection with said source and said drain; e) opening a late programming window in said second level conductive layer over said doped gate; and f) transporting said dopant from said doped gate into said channel region of said field effect transistor.
Claim 2
Independent Claim
143 words
A method for late programming integrated circuits, comprising the steps: a) forming on a silicon wafer, a field effect transistor, having a channel region defined by a source and drain, self-aligned to a gate formed from a first level conductive layer that is doped with dopant; b) depositing a first insulating layer, having an upper surface, over said field effect transistor; c) opening contact windows in said first insulating layer over said source and said drain; d) depositing a second level conductive layer on said upper surface of first insulating layer thereby filling said contact windows to make a low resistance electrical connection with said source and said drain; e) opening a late programming window in said second level conductive layer over said doped gate; and f) transporting said dopant from said doped gate into said channel region of said field effect transistor.
Claim 3
Dependent Claim
25 words
A method as recited in claim 1 further comprising, after step f), the additional step of etching said second level conductive layer to create interconnect.
Claim 4
Independent Claim
185 words
A method for late programming integrated circuits, comprising the steps: a) forming on a silicon wafer, a field effect transistor, having a channel region defined by a source and drain, self-aligned to a gate formed from a first level conductive layer that is doped with dopant; b) depositing a first insulating layer, having an upper surface, over said field effect transistor; c) opening contact windows in said first insulating layer over said source and said drain; d) depositing a second level conductive layer on said upper surface of first insulating layer thereby filling said contact windows to make a low resistance electrical connection with said source and said drain; e) said second level conductive layer is etched to define source and drain electrodes; f) depositing a second insulating layer, having an upper surface; g) depositing an initial third level conductive layer on said upper surface of said second insulating layer; h) opening a late programming window in said initial third level conductive layer over said doped gate; and i) transporting said dopant from said doped gate into said channel region of said field effect transistor.
Claim 5
Independent Claim
185 words
A method for late programming integrated circuits, comprising the steps: a) forming on a silicon wafer, a field effect transistor, having a channel region defined by a source and drain, self-aligned to a gate formed from a first level conductive layer that is doped with dopant; b) depositing a first insulating layer, having an upper surface, over said field effect transistor; c) opening contact windows in said first insulating layer over said source and said drain; d) depositing a second level conductive layer on said upper surface of first insulating layer thereby filling said contact windows to make a low resistance electrical connection with said source and said drain; e) said second level conductive layer is etched to define source and drain electrodes; f) depositing a second insulating layer, having an upper surface; g) depositing an initial third level conductive layer on said upper surface of said second insulating layer; h) opening a late programming window in said initial third level conductive layer over said doped gate; and i) transporting said dopant from said doped gate into said channel region of said field effect transistor.
Claim 6
Dependent Claim
26 words
A method as recited in claim 3 further comprising, after step h), the additional step of etching said initial third level conductive layer to create interconnect.
Claim 7
Dependent Claim
44 words
A method as recited in claim 3 further comprising, after step h), the additional steps of: g) stripping said initial third level conductive layer; h) depositing a final third level conductive layer; and i) etching said final third level conductive layer to create interconnect.
Claim 8
Independent Claim
144 words
A method for late programming integrated circuits, comprising the steps: a) forming on a silicon wafer, a field effect transistor, having a channel region defined by a source and drain, self-aligned to a gate formed from a first level conductive layer; b) doping said gate with dopant; c) depositing a first insulating layer, having an upper surface, over said field effect transistor; d) opening contact windows in said first insulating layer over said source and said drain; e) depositing a second level conductive layer on said upper surface of first insulating layer thereby filling said contact windows to make a low resistance electrical connection with said source and said drain; f) opening a late programming window in said second level conductive layer over said doped gate; and g) transporting said dopant from said doped gate into said channel region of said field effect transistor.
Claim 9
Independent Claim
144 words
A method for late programming integrated circuits, comprising the steps: a) forming on a silicon wafer, a field effect transistor, having a channel region defined by a source and drain, self-aligned to a gate formed from a first level conductive layer; b) doping said gate with dopant; c) depositing a first insulating layer, having an upper surface, over said field effect transistor; d) opening contact windows in said first insulating layer over said source and said drain; e) depositing a second level conductive layer on said upper surface of first insulating layer thereby filling said contact windows to make a low resistance electrical connection with said source and said drain; f) opening a late programming window in said second level conductive layer over said doped gate; and g) transporting said dopant from said doped gate into said channel region of said field effect transistor.
Claim 10
Dependent Claim
25 words
A method as recited in claim 6 further comprising, after step g), the additional step of etching said second level conductive layer to create interconnect.
Claim 11
Independent Claim
186 words
A method for late programming integrated circuits, comprising the steps: a) forming on a silicon wafer, a field effect transistor, having a channel region defined by a source and drain, self-aligned to a gate formed from a first level conductive layer; b) doping said gate with dopant; c) depositing a first insulating layer, having an upper surface, over said field effect transistor; d) opening contact windows in said first insulating layer over said source and said drain; e) depositing a second level conductive layer on said upper surface of first insulating layer thereby filling said contact windows to make a low resistance electrical connection with said source and said drain; f) said second level conductive layer is etched to define source and drain electrodes; g) depositing a second insulating layer, having an upper surface; h) depositing an initial third level conductive layer on said upper surface of said second insulating layer; i) opening a late programming window in said initial third layer conductive layer over said doped gate; and j) transporting said dopant from said doped, gate into said channel region of said field effect transistor.
Claim 12
Independent Claim
186 words
A method for late programming integrated circuits, comprising the steps: a) forming on a silicon wafer, a field effect transistor, having a channel region defined by a source and drain, self-aligned to a gate formed from a first level conductive layer; b) doping said gate with dopant; c) depositing a first insulating layer, having an upper surface, over said field effect transistor; d) opening contact windows in said first insulating layer over said source and said drain; e) depositing a second level conductive layer on said upper surface of first insulating layer thereby filling said contact windows to make a low resistance electrical connection with said source and said drain; f) said second level conductive layer is etched to define source and drain electrodes; g) depositing a second insulating layer, having an upper surface; h) depositing an initial third level conductive layer on said upper surface of said second insulating layer; i) opening a late programming window in said initial third layer conductive layer over said doped gate; and j) transporting said dopant from said doped, gate into said channel region of said field effect transistor.
Claim 13
Dependent Claim
26 words
A method as recited in claim 8 further comprising, after step i), the additional step of etching said initial third level conductive layer to create interconnect.
Claim 14
Dependent Claim
44 words
A method as recited in claim 8 further comprising, after step i), the additional steps of: j) stripping said initial third level conductive layer; k) depositing a final third level conductive layer; and l) etching said final third level conductive layer to create interconnect.
Claim 15
Independent Claim
44 words
A method as recited in claims 1, 2, 3, 4, 5, 6, 7, 8, 9 or 10 wherein said transporting of dopant from said doped gate into said channel region of said field effect transistor comprises diffusion in the presence of a diffusion enhancer.
Claim 16
Dependent Claim
24 words
A method as recited in claim 11 wherein said dopant is of a conductivity type opposite to that of said source and said drain.
Claim 17
Independent Claim
23 words
A method as recited in claims 11 wherein said dopant is the same conductivity type as that of said source and said drain.
Claim 18
Dependent Claim
13 words
A method as recited in claim 11 wherein said dopant comprises boron ions.
Claim 19
Dependent Claim
13 words
A method as recited in claim 14 wherein said diffusion enhancer comprises hydrogen.
Claim 20
Independent Claim
151 words
A method for late programming integrated circuits, comprising the steps: a) forming on a silicon wafer, a field effect transistor, having a channel region defined by a source and drain, self-aligned to a gate formed from a first level conductive layer that is doped with one or more dopants, including a selected dopant; b) depositing a first insulating layer, having an upper surface, over said field effect transistor; c) opening contact windows in said first insulating layer over said source and said drain; d) depositing a second level conductive layer on said upper surface of first insulating layer thereby filling said t windows to make a low resistance electrical on with said source and said drain; e) opening a late programming window in said second level conductive layer over said doped gate; and f) transporting said selected dopant from said doped gate into said channel region of said field effect transistor.
Claim 21
Independent Claim
151 words
A method for late programming integrated circuits, comprising the steps: a) forming on a silicon wafer, a field effect transistor, having a channel region defined by a source and drain, self-aligned to a gate formed from a first level conductive layer that is doped with one or more dopants, including a selected dopant; b) depositing a first insulating layer, having an upper surface, over said field effect transistor; c) opening contact windows in said first insulating layer over said source and said drain; d) depositing a second level conductive layer on said upper surface of first insulating layer thereby filling said t windows to make a low resistance electrical on with said source and said drain; e) opening a late programming window in said second level conductive layer over said doped gate; and f) transporting said selected dopant from said doped gate into said channel region of said field effect transistor.
Claim 22
Dependent Claim
25 words
A method as recited in claim 16 further comprising, after step f), the additional step of etching said second level conductive layer to create interconnect.
Claim 23
Independent Claim
193 words
A method for late programming integrated circuits, comprising the steps: a) forming on a silicon wafer, a field effect transistor, having a channel region defined by a source and drain, self-aligned to a gate formed from a first level conductive layer that is doped with one or more dopants, including a selected dopant; b) depositing a first insulating layer, having an upper surface, over said field effect transistor; c) opening contact windows in said first insulating layer over said source and said drain; d) depositing a second level conductive layer on said upper surface of first insulating layer thereby filling said contact windows to make a low resistance electrical connection with said source and said drain; e) said second level conductive layer is etched to define source and drain electrodes; f) depositing a second insulating layer, having an upper surface; g) depositing an initial third level conductive layer on said upper surface of said second insulating layer; h) opening a late programming window in said initial third level conductive layer over said doped gate; and i) transporting said selected dopant from said doped gate into said channel region of said field effect transistor.
Claim 24
Independent Claim
193 words
A method for late programming integrated circuits, comprising the steps: a) forming on a silicon wafer, a field effect transistor, having a channel region defined by a source and drain, self-aligned to a gate formed from a first level conductive layer that is doped with one or more dopants, including a selected dopant; b) depositing a first insulating layer, having an upper surface, over said field effect transistor; c) opening contact windows in said first insulating layer over said source and said drain; d) depositing a second level conductive layer on said upper surface of first insulating layer thereby filling said contact windows to make a low resistance electrical connection with said source and said drain; e) said second level conductive layer is etched to define source and drain electrodes; f) depositing a second insulating layer, having an upper surface; g) depositing an initial third level conductive layer on said upper surface of said second insulating layer; h) opening a late programming window in said initial third level conductive layer over said doped gate; and i) transporting said selected dopant from said doped gate into said channel region of said field effect transistor.
Claim 25
Dependent Claim
26 words
A method as recited in claim 18 further comprising, after step h), the additional step of etching said initial third level conductive layer to create interconnect.
Claim 26
Dependent Claim
44 words
A method as recited in claim 18 further comprising, after step h), the additional steps of: g) stripping said initial third level conductive layer; h) depositing a final third level conductive layer; and i) etching said final third level conductive layer to create interconnect.
Claim 27
Independent Claim
152 words
A method for late programming integrated circuits, comprising the steps: a) forming on a silicon wafer, a field effect transistor, having a channel region defined by a source and drain, self-aligned to a gate formed from a first level conductive layer; b) doping said gate with one or more dopants, including a selected dopant; c) depositing a first insulating layer, having an upper surface, over said field effect transistor; d) opening contact windows in said first insulating layer over said source and said drain; e) depositing a second level conductive layer on said upper surface of first insulating layer thereby filling said contact windows to make a low resistance electrical connection with said source and said drain; f) opening a late programming window in said second level conductive layer over said doped gate; and g) transporting said selected dopant from said doped gate into said channel region of said field effect transistor.
Claim 28
Independent Claim
152 words
A method for late programming integrated circuits, comprising the steps: a) forming on a silicon wafer, a field effect transistor, having a channel region defined by a source and drain, self-aligned to a gate formed from a first level conductive layer; b) doping said gate with one or more dopants, including a selected dopant; c) depositing a first insulating layer, having an upper surface, over said field effect transistor; d) opening contact windows in said first insulating layer over said source and said drain; e) depositing a second level conductive layer on said upper surface of first insulating layer thereby filling said contact windows to make a low resistance electrical connection with said source and said drain; f) opening a late programming window in said second level conductive layer over said doped gate; and g) transporting said selected dopant from said doped gate into said channel region of said field effect transistor.
Claim 29
Dependent Claim
25 words
A method as recited in claim 21 further comprising, after step g), the additional step of etching said second level conductive layer to create interconnect.
Claim 30
Independent Claim
194 words
A method for late programming integrated circuits, comprising the steps: a) forming on a silicon wafer, a field effect transistor, having a channel region defined by a source and drain, self-aligned to a gate formed from a first level conductive layer; b) doping said gate with one or more dopants, including a selected dopant; c) depositing a first insulating layer, having an upper surface, over said field effect transistor; d) opening contact windows in said first insulating layer over said source and said drain; e) depositing a second level conductive layer on said upper surface of first insulating layer thereby filling said contact windows to make a low resistance electrical connection with said source and said drain; f) said second level conductive layer is etched to define source and drain electrodes; g) depositing a second insulating layer, having an upper surface; h) depositing an initial third level conductive layer on said upper surface of said second insulating layer; i) opening a late programming window in said initial third layer conductive layer over said doped gate;, and j) transporting said selected dopant from said doped gate into said channel region of said field effect transistor.
Claim 31
Independent Claim
194 words
A method for late programming integrated circuits, comprising the steps: a) forming on a silicon wafer, a field effect transistor, having a channel region defined by a source and drain, self-aligned to a gate formed from a first level conductive layer; b) doping said gate with one or more dopants, including a selected dopant; c) depositing a first insulating layer, having an upper surface, over said field effect transistor; d) opening contact windows in said first insulating layer over said source and said drain; e) depositing a second level conductive layer on said upper surface of first insulating layer thereby filling said contact windows to make a low resistance electrical connection with said source and said drain; f) said second level conductive layer is etched to define source and drain electrodes; g) depositing a second insulating layer, having an upper surface; h) depositing an initial third level conductive layer on said upper surface of said second insulating layer; i) opening a late programming window in said initial third layer conductive layer over said doped gate;, and j) transporting said selected dopant from said doped gate into said channel region of said field effect transistor.
Claim 32
Dependent Claim
26 words
A method as recited in claim 23 further comprising, after step i), the additional step of etching said initial third level conductive layer to create interconnect.
Claim 33
Dependent Claim
44 words
A method as recited in claim 23 further comprising, after step i), the additional steps of: j) stripping said initial third level conductive layer; k) depositing a final third level conductive layer; and l) etching said final third level conductive layer to create interconnect.
Claim 34
Independent Claim
46 words
A method as recited in claims 16, 17, 18, 19, 20, 21, 22, 23, 24 or 25 wherein said transporting of said selected dopant from said doped gate into said channel region of said field effect transistor comprises diffusion in the presence of a diffusion enhancer.
Claim 35
Dependent Claim
24 words
A method as recited in claim 26 wherein said dopant is of a conductivity type opposite to that of said source and said drain.
Claim 36
Independent Claim
23 words
A method as recited in claims 26 wherein said dopant is the same conductivity type as that of said source and said drain.
Claim 37
Dependent Claim
13 words
A method as recited in claim 26 wherein said dopant comprises boron ions.
Claim 38
Dependent Claim
13 words
A method as recited in claim 29 wherein said diffusion enhancer comprises hydrogen.
References Cited (Backward Citations)
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