Late mask process for programming read only memories

Claim 2

A process for producing a custom prograrmed read-only memory (ROM) in a semiconductor wafer, comprising: fabricating in said wafer an array of MOS transistors, said MOS transistors being fabricated up to the stage of contact formation, each said MOS transistor having a source region, a drain region spaced apart from said source region, a channel region located between said source and drain region, and a gate located above and insulated from said channel region; forming a protective layer over said MOS transistors; forming an insulating layer over said protective layer, said insulating layer being of a thickness sufficient to absorb ions which are subsequently implanted; forming vias to selected ones of said source and drain regions in said transistors through said protective layer and through said insulating layer; forming electrical interconnections to said selected ones of said source and drain regions; thereafter forming a program mask on said wafer, said mask exposing those portions of said insulating layer located above the channel regions of selected transistors in said array of transistors; removing the exposed portions of said insulating layer to expose said protective layer; and implanting ions through said protective layer into said channel regions of said selected transistors to alter the threshold voltages of said selected transistors, the remaining portions of said insulating layer serving to stop passage of said ions.

Claim 3

A process in accordance with claim 1 wherein said step of implanting ions is accomplished by the step of implanting ions through said protective layer whereby the threshold voltages of said selected transistors are lowered.

Claim 4

A process in accordance with claim 1 wherein said step of implanting ions is accomplished by the step of implanting ions through said protective layer whereby the threshold voltages of said selected transistors are raised.

Claim 5

A process in accordance with claim 1 wherein said step of fabricating an array of MOS transistors is accomplished by the step of fabricating an array of MOS transistors by practicing an NMOS process.

Claim 6

A process in accordance with claim 1 wherein said step of fabricating an array of MOS transistors is accomplished by the step of fabricating an array of MOS transistors by practicing a CMOS process.

Claim 7

A process in accordance with claim 1 wherein said step of fabricating an array of MOS transistors is accomplished by the step of fabricating an array of MOS transistors by practicing a buried diffusion process.

Claim 8

A process in accordance with claim 1 wherein said step of fabricating an array of MOS transistors is accomplished by the step of fabricating an array of MOS transistors by a PMOS process.

Claim 9

A process in accordance with claim 1 wherein said step of fabricating an array of MOS transistors is accomplished by the step of fabricating an array of MOS transistors wherein each said transistor comprises a ROM cell.

Claim 10

A process in accordance with claim 1 wherein said step of fabricating an array of MOS transistors is accomplished by the step of fabricating an array of MOS transistors wherein at least one of said transistors is incorporated in a logic circuit.

Claim 11

A process in accordance with claim 1 wherein said step of forming a protecting layer is accomplished by the step of forming a layer of silicon nitride having a thickness in the range of approximately 1OOÅ to 1OOOÅ.

Claim 12

A process in accordance with claim 1 wherein said step of forming an insulating layer is accomplished by forming a layer of silicon dioxide having a thickness in the range of approximately 7,000Å 1O,OOOÅ.

Claim 13

A process in accordance with claim 1 wherein said step of forming a protective layer is accomplished by the step of forming a layer of silicon nitride.

Claim 14

A process in accordance with claim 1 wherein said step of forming an insulating layer is accomplished by the step of forming a layer of silicon dioxide.

Claim 15

A process for adjusting the threshold voltage of an MOS transistor comprising: fabricating in a semiconductor wafer an MOS transistor, said MOS transistor being fabricated up to the stage of contact formation and having a source region, a drain region spaced apart from said source region, a channel region located between said source and drain regions, and a gate located above and insulated from said channel region; forming a protective layer over said MOS transistor; forming an insulating layer over said protective layer, said insulating layer being of a thickness sufficient to absorb ions which are subsequently implanted; forming vias to selected ones of said source and drain regions through said protective layer and through said insulating layer; forming electrical interconnects to said selected ones of said source and drain regions; thereafter, applying a mask to said wafer, said mask exposing the portion of said insulating layer located above said channel region of said MOS transistor if said MOS transistor is to have its threshold voltage adjusted and said mask not exposing the portion of said insulating layer located above said channel region if said MOS transistor is not to have its threshold voltage adjusted; removing the exposed portions of said insulating layer to expose said protective layer; and implanting ions through said protective layer into said channel region of said MOS transistor if said insulating layer located above said channel region is removed, thereby altering the threshold voltage of said MOS transistor, the remaining portions of said insulating layer serving to stop passage of said ions.

Claim 16

A process for adjusting the threshold voltage of an MOS transistor comprising: fabricating in a semiconductor wafer an MOS transistor, said MOS transistor being fabricated up to the stage of contact formation and having a source region, a drain region spaced apart from said source region, a channel region located between said source and drain regions, and a gate located above and insulated from said channel region; forming a protective layer over said MOS transistor; forming an insulating layer over said protective layer, said insulating layer being of a thickness sufficient to absorb ions which are subsequently implanted; forming vias to selected ones of said source and drain regions through said protective layer and through said insulating layer; forming electrical interconnects to said selected ones of said source and drain regions; thereafter, applying a mask to said wafer, said mask exposing the portion of said insulating layer located above said channel region of said MOS transistor if said MOS transistor is to have its threshold voltage adjusted and said mask not exposing the portion of said insulating layer located above said channel region if said MOS transistor is not to have its threshold voltage adjusted; removing the exposed portions of said insulating layer to expose said protective layer; and implanting ions through said protective layer into said channel region of said MOS transistor if said insulating layer located above said channel region is removed, thereby altering the threshold voltage of said MOS transistor, the remaining portions of said insulating layer serving to stop passage of said ions.