US4329186A
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Simultaneously forming fully implanted DMOS together with enhancement and depletion mode MOSFET devices
Assignee: International Business Machines Corp
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Filing: 1979-12-20
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Granted: 1982-05-11
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Expires: 1999-12-20
Abstract
Abstract A semiconductor fabrication process and the resulting structure is disclosed for an FET device with a precisely defined channel length. Two process embodiments are described to make a diffused MOS device which does not require the use of p-type diffusions to obtain 1 micron channel length. Instead, to accurately define such micron-range channel lengths, a lateral etching technique is employed. To obtain well controlled threshold voltages, the channels are ion implanted. Thus the enhancement portion of the diffused MOS device channel is defined by an etching step instead of a diffusion step, thereby producing a channel having a length which is shorter and a threshold voltage which is better controlled than those which have been available in the prior art.
Inventors
- 👤 Harish N. Kotecha
- 👤 Francisco H. DeLaMoneda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 16:16
CPC Classifications
H; H10; H10P; H10P30/00; H10P30/20; H10P30/202; H10P30/204; H10D; H10D62/00; H10D62/10; H10D62/124; H10D62/126; H10D62/13; H10D62/149; H10D62/151; H10D62/17; H10D62/213; H10D62/221; H10D62/235; H10D62/299; H10D62/307; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/84; H10P30/21; H10P30/212; H10P76/00; H10P76/40
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
284 words
A process for forming an FET device with a precisely defined channel length on a silicon substrate of a first conductivity type on which is deposited a first layer of silicon dioxide, a layer of polycrystalline silicon, a second layer of silicon dioxide, a layer of silicon nitride and a third layer of silicon dioxide, comprising the steps of: etching said polycrystalline silicon layer, said second oxide layer, said nitride layer and said third oxide layer to form a composite gate structure having a first edge and a second edge defining a channel region for said FET device; depositing source and drain regions of a second conductivity type opposite to said first conductivity type, aligned with said first and second edges, respectively, in said substrate; laterally etching said silicon nitride layer beneath said third silicon dioxide layer, forming a reduced size silicon nitride layer having third and fourth edges displaced by a predetermined amount with respect to said first and second edges, respectively; ion implanting a first conductivity type impurity in said channel region of said substrate having a first end connected to said source region and a second end whose location is juxtaposed with said third edge of said silicon nitride layer, forming an enhancement mode portion of said channel region having a predetermined threshold voltage; implanting ions of said second conductivity type in said channel region of said substrate having a first end connected with said drain region and a second end whose location is juxtaposed with said fourth edge of said silicon nitride layer, forming a depletion region drain extension in said channel region; whereby a precisely defined effective channel length is created between said source region and said drain extension.
Claim 2
Dependent Claim
284 words
A process for forming an FET device with a precisely defined channel length on a silicon substrate of a first conductivity type on which is deposited a first layer of silicon dioxide, a layer of polycrystalline silicon, a second layer of silicon dioxide, a layer of silicon nitride and a third layer of silicon dioxide, comprising the steps of: etching said polycrystalline silicon layer, said second oxide layer, said nitride layer and said third oxide layer to form a composite gate structure having a first edge and a second edge defining a channel region for said FET device; depositing source and drain regions of a second conductivity type opposite to said first conductivity type, aligned with said first and second edges, respectively, in said substrate; laterally etching said silicon nitride layer beneath said third silicon dioxide layer, forming a reduced size silicon nitride layer having third and fourth edges displaced by a predetermined amount with respect to said first and second edges, respectively; ion implanting a first conductivity type impurity in said channel region of said substrate having a first end connected to said source region and a second end whose location is juxtaposed with said third edge of said silicon nitride layer, forming an enhancement mode portion of said channel region having a predetermined threshold voltage; implanting ions of said second conductivity type in said channel region of said substrate having a first end connected with said drain region and a second end whose location is juxtaposed with said fourth edge of said silicon nitride layer, forming a depletion region drain extension in said channel region; whereby a precisely defined effective channel length is created between said source region and said drain extension.
Claim 3
Dependent Claim
19 words
The process of claim 1 wherein said first conductivity type is p-type and said second conductivity type is n-type.
Claim 4
Dependent Claim
296 words
A process for forming an FET device with a precisely defined channel length, on a silicon substrate of a first conductivity type partitioned into device areas separated by regions of thick field oxide, a device area having a first layer of silicon dioxide, a layer of polycrystalline silicon, a second layer of silicon dioxide, a layer of silicon nitride and a third layer of silicon dioxide deposited thereon, comprising the steps of: etching said polycrystalline silicon layer, said second oxide layer, said nitride layer and said third oxide layer to form a composite gate structure having a first edge and a second edge over said device area; depositing source and drain regions of a second conductivity type opposite to said first conductivity type, aligned with said first and second edges, respectively, in said device area; laterally etching said silicon nitride layer beneath said third silicon dioxide layer, forming a reduced size silicon nitride layer having third and fourth edges displaced by a predetermined amount with respect to said first and second edges, respectively; removing said third silicon dioxide layer and ion implanting a first drain extension of said second conductivity type contiguous with said drain region, having an edge defined by said fourth edge of said silicon nitride layer; growing a fourth silicon dioxide layer around said silicon nitride layer, having edges which are aligned with said third and fourth edges of said silicon nitride layer, and removing said silicon nitride layer; ion implanting a second drain extension of said second conductivity type which is contiguous with said edge of said first drain extension, having an edge referenced with respect to said third edge of said silicon nitride layer; whereby a precisely defined channel length is created between said source region and said second drain extension.
Claim 5
Dependent Claim
296 words
A process for forming an FET device with a precisely defined channel length, on a silicon substrate of a first conductivity type partitioned into device areas separated by regions of thick field oxide, a device area having a first layer of silicon dioxide, a layer of polycrystalline silicon, a second layer of silicon dioxide, a layer of silicon nitride and a third layer of silicon dioxide deposited thereon, comprising the steps of: etching said polycrystalline silicon layer, said second oxide layer, said nitride layer and said third oxide layer to form a composite gate structure having a first edge and a second edge over said device area; depositing source and drain regions of a second conductivity type opposite to said first conductivity type, aligned with said first and second edges, respectively, in said device area; laterally etching said silicon nitride layer beneath said third silicon dioxide layer, forming a reduced size silicon nitride layer having third and fourth edges displaced by a predetermined amount with respect to said first and second edges, respectively; removing said third silicon dioxide layer and ion implanting a first drain extension of said second conductivity type contiguous with said drain region, having an edge defined by said fourth edge of said silicon nitride layer; growing a fourth silicon dioxide layer around said silicon nitride layer, having edges which are aligned with said third and fourth edges of said silicon nitride layer, and removing said silicon nitride layer; ion implanting a second drain extension of said second conductivity type which is contiguous with said edge of said first drain extension, having an edge referenced with respect to said third edge of said silicon nitride layer; whereby a precisely defined channel length is created between said source region and said second drain extension.
Claim 6
Dependent Claim
19 words
The process of claim 3 wherein said first type conductivity is p-type and said second conductivity type is n-type.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-05-10 | 1985-11-09 | 1986-05-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-05-10 | 1989-11-09 | 1990-05-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-05-10 | 1993-11-09 | 1994-05-11 | $7700.00 | Window Closed / Lapsed |