Method of making post-metal ion beam programmable MOS read only memory

Claim 3

A method according to claim 1 further including forming a plurality of other transistors and a plurality of contacts and interconnections on the face of said semiconductor body peripheral to the array, employing a mask comprising a patterned coating of photoresist through which an ion beam is directed in selectively ion implanting the cells in accomplishing programming of the array of memory cells, and wherein the programming occurs after said contacts and interconnections have been formed.

Claim 4

A method according to claim 2 wherein the field effect transistors and the other transistors are P-channel metal gate transistors.

Claim 5

A method according to claim 2, wherein the field effect transistors and the other transistors are P-channel silicon gate transistors, and the forming of contacts and interconnections peripheral to the array is accomplished by depositing metal in a thin film and patterning the metal film.

Claim 6

A method according to claim 1 wherein the step of programming by ion implant produces trapping centers in the oxide.

Claim 7

A method according to claim 1 further including forming a plurality of other transistors and a plurality of contacts and interconnections on the face of said semiconductor body peripheral to the array, employing a mask comprising a patterned coating of photoresist through which an ion beam is directed in selectively ion implanting the cells in accomplishing programming of the array of memory cells and including implanting through the gate electrodes and into the gate oxide of said plurality of other transistors, and wherein the programming occurs after said contacts and interconnections have been formed.

Claim 8

A method according to claim 2 wherein the field effect transistors and the other transistors are N-channel silicon gate transistors, and the forming of said contacts and interconnections peripheral to the array is accomplished by depositing metal in a thin film and patterning the thin metal film.

Claim 9

A method according to claim 2 wherein the field effect transistors and other transistors are N-channel metal gate transistors.

Claim 10

In a method of making a read-only-memory which includes the steps of: forming a plurality of insulated gate field effect transistors in the face of a semiconductor body, each of the transistors having spaced source and drain regions, a channel between the source and drain regions, a gate oxide layer overlying the channel between the source and drain regions, and a gate electrode overlying the gate oxide, the transistors being in a regular pattern to provide an array of memory cells; forming a plurality of other transistors and a plurality of contacts and interconnections on said face of said semiconductor body peripheral to the array; the improvement comprising: ion implanting particular memory cells by directing ions of sufficient energy to directly penetrate through the material of the gate electrode and into the gate oxide of selected memory cells using a mask applied after said contacts and interconnections have been formed; and programming the array of memory cells by altering the electrical characteristics of said particular memory cells in response to the selective ion implantation of said particular memory cells.

Claim 11

In a method of making a read-only-memory which includes the steps of: forming a plurality of insulated gate field effect transistors in the face of a semiconductor body, each of the transistors having spaced source and drain regions, a channel between the source and drain regions, a gate oxide layer overlying the channel between the source and drain regions, and a gate electrode overlying the gate oxide, the transistors being in a regular pattern to provide an array of memory cells; forming a plurality of other transistors and a plurality of contacts and interconnections on said face of said semiconductor body peripheral to the array; the improvement comprising: ion implanting particular memory cells by directing ions of sufficient energy to directly penetrate through the material of the gate electrode and into the gate oxide of selected memory cells using a mask applied after said contacts and interconnections have been formed; and programming the array of memory cells by altering the electrical characteristics of said particular memory cells in response to the selective ion implantation of said particular memory cells.

Claim 12

In a method according to claim 9, wherein the field effect transistors and the other transistors are P-channel metal gate transistors.

Claim 13

In a method according to claim 9, wherein the field effect transistors and the other transistors are P-channel silicon gate transistors, and the formation of at least some of the contacts and interconnections is accomplished by depositing metal in a thin film and patterning the metal film.

Claim 14

In a method according to claim 9, wherein the step of programming includes ion implanting through the gate electrodes and into the gate oxide of said plurality of other transistors.

Claim 15

In a method according to claim 12, wherein the field effect transistors and the other transistors are N-channel silicon gate transistors, and the formation of at least some of the contacts and interconnections is accomplished by depositing metal in a thin film and patterning the metal film.

Claim 16

In a method according to claim 9, wherein the field effect transistors and other transistors are N-channel metal gate transistors.

Claim 19

A method according to claim 15 wherein the ion implantation of particular memory cells is carried out by implanting ions into the gate electrode of each selected memory cell and to a depth at least into the gate oxide, and inducing a charge in the respective gate oxides of each selected memory cell in response to the implantation of ions thereinto.